We present measurements of transmission of infrared radiation through double-layer metallic grating structures. Each metal layer contains an array of subwavelength slits and supports transmission resonance in the absence of the other layer. The two metal layers are fabricated in close proximity to allow coupling of the evanescent field on individual layers. The transmission of the double layer is found to be surprisingly large at particular wavelengths, even when no direct line of sight exists through the structure as a result of the lateral shifts between the two layers. We perform numerical simulations using rigorous coupled wave analysis to explain the strong dependence of the peak transmission on the lateral shift between the metal layers.

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This paper describes the fabrication, and structural and electrical characterization of a new, aerosolnanocrystal floating-gate FET, aimed at non-volatile memory (NVM) applications.This aerosolnanocrystal NVM device features prograderase characteristics comparable to conventional stacked gate NVM devices, excellent endurance (>lo5 P/E cycles), and long-term non-volatility in spite of a thin bottom oxide (55-60A). In addition, a very simple fabrication process makes this aerosol-nanocrystal NVM device a potential candidate for low cost NVM applications.Introduction The memory operation of the aerosol-nanocrystal floating-gate FET depends on charge storage, similar to conventional stacked-gate NVM devices [l]. In a nanocrystal NVM device, however, charge is not stored on a continuous floating-gate poly-Si layer, but instead on a layer of discrete, crystalline Sinanocrystals [2-41. As compared to conventional stacked-gate NVM devices, nanocrystal chargestorage offers several potential advantages such as: (1) simple, low cost device fabrication (no dual-poly process complications); (2) better retention (resulting from Coulomb blockade and quantum confinement effects fS]), enabling thinner tunnel oxides and lower operating voltages; ( 3 ) improved anti-punchthrough performance (due to the absence of drain to floating gate coupling, thereby reducing drain induced punchthrough), allowing higher drain voltages during read-out, shorter channel lengths and, consequently, a smaller cell area; and (4) excellent immunity to stress induced leakage current (SILC) and defects due to the distributed nature of the charge storage in the nanocrystal layer. Device Fabrication Nanocrystal layer fabricationThis potential for cost reduction and improved device performance and reliability is, however, strongly dependent on the physical properties of the nanocrystal layer, such as the crystal size and size distribution, crystal areal density, layer co-planarity and uniformity, and crystal-to-crystal interaction (lateral conduction). In order to achieve the desired layer properties, a novel, three-step nanocrystal fabrication process has been developed (Fig. 1). In the first step, a nanocrystal silicon aerosol is generated by the pyrolysis of diluted silane at 950°C. Particles initially form by homogeneous gas-phase nucleation and grow by vapor deposition and coagulation. The coagulation has been reduced by quenching the aerosol with an ultrahigh-purity nitrogen flow.Silane concentration, furnace temperature and silane residence time have all been optimized in order to generate an aerosol of spherical, single crystalline nanocrystals (Fig. 2, inset) with well-controlled diameters (Fig. 3) as small as 3nm. In the second step, a 1.5-2nm high-quality thermal oxide shell is grown at 1000°C on the particles. This insulating shell reduces lateral crystal-to-crystal conduction in the nanocrystal layer. The oxidation step has the additional advantage of sharpening the

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