with On-Chip L2 Cache Controller NexGen, Inc., Milpitas, CA This 3.5M-transistor microprocessor uses a 0 . 5~ CMOS technology (Table 1). The die is mounted on the package with a solderbump technology. Using custom and routed blocks with 5-layer metal, a die size of 14.1x14.1mmz is produced as shown in Figure 1. At 4.0V and 25"C, the chip operates above 93MHz. With a 1MB cache of 1211s S u s , performance is over 12OWinstones.
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