Router flip chip packaging solution and reliability

2012 IEEE 62nd Electronic Components and Technology Conference

Motalab

Hussain

et al. 2012

Section: Introductionmentioning

confidence: 98%

Measurement of die stresses in microprocessor packaging due to thermal and power cycling

2012 IEEE 62nd Electronic Components and Technology Conference

Motalab

Hussain

et al. 2012

“…Over the past few years, the flip chip solder interconnects have transitioned to full area arrays and lead free composition, while the size of the processor die has grown dramatically. In addition, the utilized Ceramic Ball Grid Array (CBGA) substrates are now typically constructed from "high CTE" glass ceramic materials [1][2][3][4][5][6][7]. Relative to the older alumina ceramic technology with tungsten based conductors, these new ceramics have significantly higher coefficients of thermal expansion (10-12 ppm/C) and much lower stiffnesses (70-80 GPa).…”

Section: Introductionmentioning

confidence: 99%

Measurement of die stress distributions in flip chip CBGA packaging

2010 12th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems

Hussain

Rahim

et al. 2010

On-chip piezoresistive stress sensors represent a unique approach for characterizing stresses in silicon die embedded within complicated packaging architectures. In this work, we have used test chips containing such sensors to measure the stresses induced in microprocessor die after various steps of the assembly process, as well as the stress changes occurring due to thermal cycling. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 x 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers.Before packaging, the sensor resistances were measured by directly probing the test chip wafers. The chips were then diced, reflowed to the ceramic substrate, and then underfilled and cured. Finally, a metallic lid was attached to complete the ceramic LGA package. After every packaging step (solder reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. A set of low stress test fixtures was developed to eliminate clamping induced stresses being generated during the sensor resistance measurements.

Section: Introductionmentioning

confidence: 99%

Stress measurements in large area array flip chip microprocessor chips

2008 58th Electronic Components and Technology Conference

Rahim

Suhling

et al. 2008

Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configuration features a complex stack up of area array solder interconnects, underfill, ceramic substrate, lid, heat sink, thermal interface materials, second level solder joints, organic PCB, etc., so that a very complicated set of loads is transmitted to the microprocessor chip. Several trends in the evolution of this packaging architecture have exacerbated die stress levels including the transition to larger die, high CTE ceramic substrates, lead free solder joints, higher level of power generation, and larger heat sinks. Die stress effects are of concern due to the possible degradation of silicon device performance (mobility/speed) and due to the possible damage that can occur to the copper/low-k top level interconnect layers.In this work, we have used test chips containing piezoresistive sensors to measure the stresses induced in microprocessor die after various steps of the assembly process. The utilized (111) silicon test chips were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 x 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to the high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the stress test die. The chips were reflowed to the ceramic substrate, and then underfilled and cured. Finally, a metallic lid was attached to complete the ceramic LGA package. After every packaging step (solder reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. The build-up of the die stresses was found to be monotonically increasing, and the relative severity of each assembly step was judged and compared. Such an approach allows for various material sets (solders, underfills, TIM materials, lid metals, and lid adhesives) to be analyzed and rated for their contribution to the die stress level.