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The Department of Defense (DoD) Goal Security Architecture (DGSA) introduces a broader view of information security from that previously held by the Department, one which has much more in common with the requirements of an inter-networked commercial view of information security. The purpose of this paper is to introduce designers of operating systems to the most important aspects of the DGSA conceptual framework in order to open discussions on both the suitability of the framework and the feasibility of its implementation. The rationale for this framework is discussed in this paper. Challenging aspects of implementation are presented, and areas needing refinement prior to operating system implementation are described.Work supported by the National Security Agency and the Defense Information Systems Agency under contract number DASW01-94-C-0054. The views expressed in this article are those of the authors and do not reflect the official policy or position of the Department of Defense or the U.S. Government.

The purpose of this paper is to describe the concepts, definitions, and ideas of computer architecture and to suggest that architecture can be viewed as composed of three components: physical organization; control and flow of information; and representation, interpretation and transformation of information. This framework can accommodate diverse architectural concepts such as array processing, mieroprogramming, stack processing and tagged architecture. Architectures of some existing machines are considered and methods of associating architectural concepts with the components are established. Architecture design problems and trade-offs are discussed in terms of the proposed framework. Address Address 20 bits Smgle Address ] Program couple control word (PCW) Address J Return control couple word (RCW) Indirect Address J reference * S. S. Reddi and E. A. Feustel

Vector processors, parallel processors, and sequential processors with much concurrency are considered. Some real codes can be shown to be almost completely suitable for parallel and vector processors. However, vector to scalar speed ratios can be so large for the vector and parallel machines that even a small residual scalar content is a serious problem. Monte Carlo approaches and Implicit differencing schemes yield shorter vectors than explicit differencing schemes, causing problems due to long vector operation start up times.Programming in a vector language may be a more global and easier to understand approach to programming. It is necessary to use such an approach In order to attain some reasonable frac tion of the potential speed of a vector or parallel processor, Introduction and Summary

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