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In this paper, a complete example for BIST (Built-In Self-Test) boundary scan architecture and 16-bit multiplier as the CUT is presented. Adding BIST boundary scan capabilities to the digital VLSI integrated circuit design makes the electronic card testable from five pins TMS, TCK, TDI, TDO and TRST* that is optional. The simulation and then design download are presented on the Spartan Xilinx X2C100 chip. The hardware implementation is tested using the interfacing through the parallel port of the personal computer that supplies required five control pins. This approach will lead to the concept of the portable ATE (Automatic Test Equipment). All required test circuitry is embedded in the integrated circuits and the control of the test circuitry is supplied from the TAP (Test Access Port) controller. Finally, the TAP controller is controlled from the parallel port of the personal computer. So, the personal computer is used as a master controller and the TAP controller is used as a slave controller. The presented idea of the new BIST testing architecture solves the testing problem of the digital VLSI circuits using the traditional ATE.

The demand for efficient, real time video cryptography systems has become more prominent in our life, especially for military and sensitive-civilian applications. FPGA implementation of video cryptography systems is suitable for both video and cryptography processes due to video data rate, flexibility to design modifications, and cryptography algorithm agility. In this paper, a bulk video cryptography system using AES (Advanced Encryption Standard) is designed and implemented on low cost FPGA Xilinx Spartan-III™. Bulk encryption is used to encrypt both video data and video synch to increase the cryptanalysis complexity for intruders. The design is implemented on different stages; camera interface, video frame grabber, VGA monitor interface, SDRAM controller, crypto processor, and communication channel interface. The design has been tested first using a generated video pattern, and using external composite PAL/NTSC video camera source. The design is implemented for XC3S1000 and the results were significant for speed 1 Master Student, R&D Center, Egyptian Air Forces.

The demand for efficient, real time video cryptography systems has become more prominent in our life, especially for military and sensitive-civilian applications. The proposed system design was constrained in both area and speed in order to fulfill the requirements for real time video signals with limited hardware resources. Using Field Programmable Gate Array (FPGA) for the system implementation is suitable for both video and cryptography processes due to video data rate, flexibility to design modifications, and cryptography algorithm agility. The design strategy was based on making use of all available pre-designed, pre-verified cores for low cost Xilinx Spartan III XC3S1000-ft256 FPGA chip. In this system, only active video data are encrypted with (Rijndael) Advanced Encryption Standard (AES) crypto algorithm and a self-synchronized cipher key mechanism based on the embedded video Timing Reference Signals (TRS) was designed to overcome the security leakage in Electronic Codebook (ECB) mode and to reduce the possibilities of cryptanalytic attacks which are used to recover the encryption key like brute force attacks. The design is tested first using an internally generated video pattern, then using external composite video camera source. The design implementation results were significant for speed and area, it reached 59.044 Mbytes/sec. data throughput that fulfills the minimum requirements of colorful, 30 FPS video data rate of 27 Mbytes/sec., and the design occupies 4,007 slices (52% of chip size).