Microcontrollers have become a widely accepted architecture for highly complex embedded systems on a single chip (SoC). It consists of deeply embedded heterogeneous components with poor accessibility makes their testing process a difficult task using hardware based self-test (HBST). Software-based self-test (SBST) is considered to be a promising testing technology for these systems. Almost every SoC contains at least one embedded processor, SBST utilize this processor for test pattern generation (TPG) and test response compaction (TRC) based on its instruction set, then test response will be unloaded and evaluated using external automatic test equipment (ATE). In this paper, SBST strategy disadvantages in microcontroller testing will be identified. Then, a new testing approach that combines both the HBST and the SBST, called hybrid-based self-test (HYBST) will be introduced. Based on a divide-and-conquer approach, HYBST identify microcontroller's components and their corresponding component operations. Feasibility and effectiveness of HYBST and SBST methodologies will be assessed by applying them to a Microchip ® PIC16F877A and PIC18F452 in terms of memory usage, time consumption and number of tested modules found in microcontrollers.

The authors in paper [1] are presented the new automatic test equipment (ATE) for digital integrated circuits based on the signature analysis. This work introduced a complete framework for the testing of the printed circuit boards (PCBs) of the digital integrated circuits. In this paper, the Field Programmable Gate Array (FPGA) implementation of this new ATE is presented. The timing simulation and then design download are presented on the Spartan Xilinx chip (X2S400EFT256-7). In this paper, the concept of the portable ATE is presented that reduces the complexity of the traditional ATE. This compacted testing system approach is designed to apply the test pattern to the circuit under test (CUT) and to compact the response of the CUT by signature analyzer. The timing controller and the parallel port of the personal computer (PC) generate all required signals to control all steps of the test cycle for proper operation.

Several authors focused on testing of digital integrated circuits and their different test scenarios are proposed. No author speaks about the testing of the monostable multivibrator on the board. In this paper, a novel circuit design methodology is presented to test the monostable multivibrators functionally on the board. To test the monostable multivibrators properly, the time duration needs to be measured accurately. This method is based on the signature generation of the output of the monstable multivibrators. The measurement of the time duration is considered the signature that expresses the proper functionality of the monstable multivibrators. This testing design was implemented and applied to different pulse durations. The experimental results indicate the high accuracy of the proposal design approach. The measurements in the millisecond range had not any deviation from the setting pulse. The measurements in the microsecond range had small deviation from the setting pulse ± 1%.

Testing for delay and CMOS stuck-open faults requires two-pattern tests. Built-in self-test (BIST) schemes are required to comprehensive testing of such faults. BIST test pattern generators for two-pattern testing should be designed to ensure high transition coverage. The test pattern generator (TPG) circuits treated here are not limited to linear feedback shift registers (LFSRs) but include autonomous linear feedback shift register / shift register (LFSR/SR) circuits. It is required to increase the number of each subset of the state variables for complete transition coverage with the optimal test lengths.In this paper, the two-pattern test capabilities of LFSR/SRs are explored using transition coverage as the metric. The necessary and sufficient conditions to ensure complete transition coverage for LFSR/SRs are derived. The theory developed here identifies all LFSR/SR TPGs that determine the complete transition coverage under any given TPG size constraint. It is shown that LFSRs with primitive feedback polynomials with large number of terms are better for twopattern testing. Based on the necessary and sufficient conditions, two-pattern testing have been developed. Experiments indicate that TPGs designed using the procedures outlined in this paper obtain high robust path delay fault coverage with the optimal shortest test lengths.

The aim of this paper is to design and develop a low-cost prosthetic arm based on surface electromyography (sEMG) signal activities of the biceps muscle during upper-limb movement. Different methods are described in the literature, but many problems are encountered in dealing with the online processing of raw EMG (rEMG) signals, such as signal sampling and memory requirements. In this paper, the enveloped EMG (eEMG) signal is used as a control signal that reduces signal sampling rate and memory requirements. The relationship between elbow motion and the activity level of the biceps muscle is characterized using relevant extracted features (root mean square (RMS)). Validation of the proposed low-cost system is conducted using comparison with a professional biomedical system (Bioback MP150). In addition, the estimated equation of movements of each subject is estimated based on the recorded data. From this equation, the angle of motion is calculated as the control of the movement of the robotic arm. Finally, the system proposed in this paper considers the eEMG signal rather than the rEMG signal and deals with the signal based on a sample of 1 KHz rather than 10 KHz. This system reduces our target cost (reduction in hardware requirements and processing time) with acceptable accuracy. The experimental results illustrate that the eEMG signal has the same features-print as that of the rEMG signal, and the eEMG signal can generate the control signal required to move the prosthetic arm.