Two-Pattern Test Capabilities of Autonomous LFSR/Sr Generator in Pseudo-Exhaustive Testing

Abstract

Testing for delay and CMOS stuck-open faults requires two-pattern tests. Built-in self-test (BIST) schemes are required to comprehensive testing of such faults. BIST test pattern generators for two-pattern testing should be designed to ensure high transition coverage. The test pattern generator (TPG) circuits treated here are not limited to linear feedback shift registers (LFSRs) but include autonomous linear feedback shift register / shift register (LFSR/SR) circuits. It is required to increase the number of each subset of the state variables for complete transition coverage with the optimal test lengths.In this paper, the two-pattern test capabilities of LFSR/SRs are explored using transition coverage as the metric. The necessary and sufficient conditions to ensure complete transition coverage for LFSR/SRs are derived. The theory developed here identifies all LFSR/SR TPGs that determine the complete transition coverage under any given TPG size constraint. It is shown that LFSRs with primitive feedback polynomials with large number of terms are better for twopattern testing. Based on the necessary and sufficient conditions, two-pattern testing have been developed. Experiments indicate that TPGs designed using the procedures outlined in this paper obtain high robust path delay fault coverage with the optimal shortest test lengths.

New Hybrid-Based Self-Test Strategy for Faulty Modules of Complex Microcontroller Systems

“…In addition, and due to the small numbers of input modules in the microcontroller, the exhaustive testing is used to detect all combinational faults, detected by single-pattern test generators without fault simulator [1], [13]. Therefore, the proposed test strategy is not suitable for the detection of the delay fault, detected by two-pattern test generators without fault simulator [12]. It is required to expand the following proposal to the two-pattern test generators, presented in [12].…”

“…Therefore, the proposed test strategy is not suitable for the detection of the delay fault, detected by two-pattern test generators without fault simulator [12]. It is required to expand the following proposal to the two-pattern test generators, presented in [12]. This extension will increase the required hardware overhead in the memory utilization and will increase the required number of the clock cycles.…”

“…The presented test strategy in this paper is based on exhaustive testing for test pattern generation to achieve high structural fault coverage for each module of the microcontroller. It detects all detectable combinational faults detected by single-test pattern without using the fault simulator [1], [5], [6], [12]- [13]. The next sections present the fourth phase.…”

“…The easiest way to test a small circuit is to apply all possible test patterns, called exhaustive testing. This testing is not practical for large circuits [1], [12]- [13]. The more common approach for testing is to use computer algorithms for automatic test pattern generation (ATPG) [2]- [3], [5], [14]- [15].…”

“…Generation of these test subroutines requires knowledge of the ISA of the microcontroller. The exhaustive testing guarantees the detection of all detectable combinational faults, detected by single-pattern test generator [1], [12]- [13]. This leads to achieve high fault coverage without performance degradation and without fault simulator.…”