Testing for delay and CMOS stuck-open faults requires two-pattern tests. Built-in self-test (BIST) schemes are required to comprehensive testing of such faults. BIST test pattern generators for two-pattern testing should be designed to ensure high transition coverage. The test pattern generator (TPG) circuits treated here are not limited to linear feedback shift registers (LFSRs) but include autonomous linear feedback shift register / shift register (LFSR/SR) circuits. It is required to increase the number of each subset of the state variables for complete transition coverage with the optimal test lengths.In this paper, the two-pattern test capabilities of LFSR/SRs are explored using transition coverage as the metric. The necessary and sufficient conditions to ensure complete transition coverage for LFSR/SRs are derived. The theory developed here identifies all LFSR/SR TPGs that determine the complete transition coverage under any given TPG size constraint. It is shown that LFSRs with primitive feedback polynomials with large number of terms are better for twopattern testing. Based on the necessary and sufficient conditions, two-pattern testing have been developed. Experiments indicate that TPGs designed using the procedures outlined in this paper obtain high robust path delay fault coverage with the optimal shortest test lengths.

Integrated circuits (ICs) are reaching complexity that was hard to imagine. ICs incorporating hundreds of millions of transistors, mega-bit memories, complicated pipelined structures, etc., are in high demand. Obviously, designing such complex circuits poses real challenges to engineers. Certainly, no relief comes from the competitive marketplace, with increasing demands for a very narrow window of time (time-to-market) in engineering a ready product. Therefore, a systematic and well-structured approach to designing ICs to be testable is a must. With the growth in complexity of very large scale integration (VLSI) circuits, test generation for circuits is becoming increasingly difficult and time consuming. Even though the computing power and resources have multiplied dramatically over last few decades, an increasing number of memory elements in VLSI circuits require more effective and powerful sequential test generators. This paper is represented to review concepts and techniques for testing electronic circuits and systems as part of a lecture review. This covers various testing and design-for-test (DFT) techniques starting from (Automatic Test Equipment) ATE basics (definition, construction and types). Exploring testing strategies for digital combinational and sequential circuits, and introduces a comparative study between the common fault models. Finally the paper ends with design for testability guiding rules and possible challenges and difficulties that need development and research in the testing problem.