Hardware in the loop simulation has become a fundamental tool for the safe and rapid development of embedded systems. Dynamically and partially reconfigurable FPGA provide an energy efficient solution for high performance computing in embedded systems, such as computer vision, with limited resources. Finally 3D simulation with realistic physics simulation is required by designers of Unmanned Aerial Vehicle (UAV) and related missions. The combination of the three techniques are required to design UAV with reconfigurable HW/SW embedded systems that can self-adapt to different mission phases according to environment changes. But they require different complex and specific skills from separated communities and so are not considered simultaneously. In this paper we demonstrate a complete framework that we apply to a UAV case simulated with the well adopted Gazebo 3D simulation tool including the Ardupilot model. According to usual practices in Robotics, we use Robot Operating System (ROS) middleware over Linux that we implement on a separated Intel Cyclone V FPGA board including HW/SW interfaces. As a convincing case study we implement, besides software classical navigation tasks, a vision-based emergency-landing security task and a detect and tracking classic mission application (TLD) that can run in different HW and SW versions dynamically configured on the FPGA according to mission steps simulated with Gazebo.

An ever larger share of FPGAs are supporting Dynamic and Partial Reconfiguration (DPR). A reconfigurable point-to-point interconnect (ρ-P2P) is a communication mechanism based on DPR that swaps between different precomputed configurations stored in partial bitstreams. ρ-Point-to-Point (P2P) is intended as a lightweight interconnect that suits the reconfigurable systems where a limited number of configurations are desirable. This paper assesses the pros and cons of ρ-P2P in terms of resource and performance depending on the number of input/output signals, their width and the number of supported configurations.Experimental results, conducted on an Intel Cyclone V FPGA, compare ρ-P2P to an equivalently functional non-DPR solution called µ-P2P and to a full crossbar. They show that ρ-P2P is indeed lightweight but introduces performance limitations on operating frequency, memory footprint and reconfiguration time. However, ρ-P2P is in general the least resource intensive of the tested interconnects, except in the trivial case of low numbers of signals and configurations. In particular, an 18 × 18 full crossbar interconnect requires 75% more resources than an equivalent ρ-P2P. Interestingly, this resource difference between ρ-P2P and a full crossbar grows linearly with the interconnect size.

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