Based on the QorlQ ® system-on-chip processor architecture from Freescale Semiconductor with additional unique features for space applications, the RAD55xX™ system on-chip platform integrated circuit can be personalized into multiple processor solutions. The RAD55xx platform includes four 32/64 bit Power Architecture ® processor cores, three levels of on-die cache memory, dual interleaved DDR3 DRAM controllers, data path acceleration architecture (DPAA) on-die hardware accelerators, a NAND Flash controller, and high I/O throughput based on serializer/deserializer high speed links. Manufactured at the IBM trusted foundry in 45nm silicon-on insulator (SOl) process technology with copper interconnect and leveraging the radiation-hardened by design RH45™ technology, the RAD55xx platform optimizes power/performance to deliver processor throughput of up to 5.6 GOPS/3.7 GFLOPS, memory bandwidth of up to 102 Gb/s, and I/O throughput of up to 64 Gb/s. Each of the highly efficient RAD5500™ 64-bit cores offers direct addressability to 64 GB of memory, improves double precision floating point performance, and achieves 3.0 Dhrystone MIPS/MHz. The RAD55xx platform is designed for insertion into systems using the SpaceVPX standard, supporting the RapidlO data plane, SpaceWire control plane, and 12C utility plane. Architectural trades, the development methodology, technical challenges, and single board computer solutions are discussed.

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A BiCMOS gate array with nearly the same density as CMOS arrays has been realized using an advanced 1.5 um BiCMOS process and a channelless architecture, A two input BiCMOS NAND gate has a delay of 800 ps when driving a load of sixteen which is half the delay in CMOS. Arrays with up to 123K equivalent gates can be achieved with a optimal ratio of CMOS logic gates and BiCMOS blocks. 20.6.1 IEEE 1988 CUSTOM INTEGRATED CIRCUITS CONFERENCECH2584-1/88/0000-0119 $1.00 0 1988 IEEE

A marked state dependence and significant reduction in SEU cross section with even small increases in incident angle are reported in an asymmetric RC-hardened 90 nm CMOS SRAM. The effects are attributable to the bias dependence and high aspect ratio of the deep trench capacitor sidewall depletion region, exacerbated by process-induced boron depletion. The asymmetric implementation, using capacitive hardening in only one leg of the SRAM cell, led to the appearance of the effect in experimental results.