A high density BiCMOS direct drive array

Abstract

A BiCMOS gate array with nearly the same density as CMOS arrays has been realized using an advanced 1.5 um BiCMOS process and a channelless architecture, A two input BiCMOS NAND gate has a delay of 800 ps when driving a load of sixteen which is half the delay in CMOS. Arrays with up to 123K equivalent gates can be achieved with a optimal ratio of CMOS logic gates and BiCMOS blocks. 20.6.1 IEEE 1988 CUSTOM INTEGRATED CIRCUITS CONFERENCECH2584-1/88/0000-0119 $1.00 0 1988 IEEE

Gate usage strategies applied to BiCMOS sea-of-gates arrays

“…Hence, for each configuration C, DEL = delayc(FI, CL) is also a random variable, and its distribution fDEL(de1) can be calculated [5]:…”

“…BiCMOS TP buffers are used only for a small number of heavily loaded nodes, such as clocks. In that case, the master core is a CMOS sea-of-gates, surrounded by a small area dedicated to BiCMOS buffers [5].…”