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In this work, an efficient implementation of a programmable Finite Impulse Response (FIR) filter based on the use of the Karatsuba Multiplication Algorithm (KMA) is presented. In this FIR filter circuit, a parallel, Modified Booth (MB) pre-encoded, Carry-Save (CS) Wallace tree multiplier is used as a building block. The KMA is a fast divide and conquer algorithm for the multiplication of large numbers. As a result, the proposed circuit is highly efficient in terms of speed, area and power in comparison with the Conventional FIR filter architecture. Simulations of FIR filters in transposed form made over standard-cell implementation based on a Faraday 90nm technology show an average reduction of about 15% in the delay, 9% in area and 17% in power. Keywords-Finite impulse response (FIR) filter; Karatsuba algorithm; VLSI DesignI.

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