Hardware efficient fast FIR filter based on Karatsuba algorithm

Kyritsis, Evangelos; Pekmestzi, Kiamal

doi:10.1109/mocast.2016.7495158

Cited by 3 publications

References 4 publications

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Review on Fir Filter Architecture Design and its Computational Blocks

Satyanarayana

Reddy

Ravi

et al. 2019

IOP Conf. Ser.: Mater. Sci. Eng.

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Low power VLSI circuit employed applications power consumption and high performance, the area is crucial in DSP. A filter is used in almost all electronic devices that function on signals. They are used to extract the useful part from the input signal and the required part of signal reaches the receiver. This paper is mainly focussed on the survey of different architecture design for FIR filter. The different performances such as speed, complexity, PDP, ADP, are reviewed.

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Review on Fir Filter Architecture Design and its Computational Blocks

Satyanarayana

Reddy

Ravi

et al. 2019

IOP Conf. Ser.: Mater. Sci. Eng.

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A Practical Energy/Power Reduction Approach for Parallel Decimal Multiplier

2022

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Decimal computation is highly demanded in many human-centric applications such as banking, accounting, tax calculation, and currency conversion. Hence the design and implementation of radix-10 arithmetic units attract the attention of many researchers. Among the basic decimal arithmetic operations, multiplication is not only a frequent operation but also has high complexity and considerable power consumption. Therefore, this paper concentrates on this issue and studies a general design methodology that reduces power/energy consumption via localizing switching activity without compromising target performance. This method decomposes a digit multiplier into smaller ones, like Karatsuba's algorithm, while the multiplicand and the multiplier can be partitioned into different sizes. We take advantage of various size partitions in two types of symmetric and asymmetric, which final designs provide specific characteristics. All designs were implemented using VHDL and synthesized in the Design-Compiler toolbox with TSMC 130 nm Technology file. The results are significant; in respect to the original design, by a random test vector, 25% power reduction is achieved with no effect on latency and a negligible area penalty. Moreover, the experimental results indicate a potential for considerable reduction of power dissipation based on statistical properties of possible input data.INDEX TERMS Decimal computation, Digital arithmetic, Low power design, Parallel multiplier.

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Area efficient and speed performance of pre encoded multiplier by using non redundant radix-4 signed digit encoding

Bhore

Thakare

2017

2017 International Conference of Electronics, Communication and Aerospace Technology (ICECA)

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Hardware efficient fast FIR filter based on Karatsuba algorithm

Cited by 3 publications

References 4 publications

Review on Fir Filter Architecture Design and its Computational Blocks

Review on Fir Filter Architecture Design and its Computational Blocks

A Practical Energy/Power Reduction Approach for Parallel Decimal Multiplier

Area efficient and speed performance of pre encoded multiplier by using non redundant radix-4 signed digit encoding

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