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Image rejection ratio in double balanced mixers is strongly dependent on the balance between its branches. The influence of mismatches is analysed and conclusions on the key aspects of the design to increase the image rejection are discussed. A practical circuit implementation is described: a I.9GHz downconversion image rejection mixer is fabricated in 0 . 6~ CMOS standard technology. Measurements on the prototype showed a 34dB image rejection and an overall conversion gain of 16dB.Proceedings SBMOIIEEE M I T S IMOC 2W3

The design and simulation of a dual-band monolithic low noise amplifier, with active balun and gain control integrated on the same die, is presented on this paper. The circuit includes an internal DAC, allowing sixteen gain levels with digital control. The fully integrated circuit was implemented in a 0.35µm AMS CMOS standard technology and simulated with BSIM3 model. Simulations show a 16dB (1dB/step) dynamic gain variation in a 1.4-1.7GHz band (includes dual sub-bands), a phase and transducer gain magnitude errors less than 1.6º and 0.2dB, respectively, a 1.24dB noise figure and -23dBm input-referred 1dB compression point both at maximum gain, 50Ω input and output match, while drawing less than 7.5mA from a 1.7V power supply, including analog and digital system.

Abstract:The development of high performance monolithic RF front-ends requires innovative RF circuit design to make the best of a good technology. A fully differential approach is usually preferred, due to its well-known properties. Although the differential approach must be preserved inside the chip, there are cases where the input signal is single-ended such as RF image filters and IF filters in a RF receiver. In these situations, a stage able to convert single-ended into differential signals (balun) is needed. The most cited topology, which is capable of providing high gain, consists on a differential stage with one of the two inputs grounded. Unfortunately, this solution has some drawbacks when implemented monolithically. This work presents the design and simulated results of an innovative high-performance monolithic single to differential converter, which overcomes the limitations of the circuits.The integration of the monolithic active balun circuit with an LNA on a 0.18μm CMOS process is also reported. The circuits presented here are aimed at 802.11a. Section 2 describes the balun circuit and section 3 presents its performance when it is connected to a conventional single-ended LNA. Section 4 shows the simulated performance results focused at phase/amplitude balance and noise figure. Finally, the last section draws conclusions and future work.