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SUMMARYCurrent reuse low-noise-amplifiers (CRLNAs) have been the norm to achieve high-gain and low-noise figure under low-power budgets. However, conventional CRLNAs suffer from a severe lack of large-signal linearity, especially in conventional cascaded CRLNAs. This main drawback is related with the typical biasing method imposed in the output stage. To prove our point, a large-signal study is performed for a single stage commonsource in two distinct biasing situations: voltage biased and current biased. On the basis of the gathered results, a new CRLNA solution is proposed to relief the large-signal bottleneck. The suggested design is analyzed in a 0.13 μm complementary metal-oxide-semiconductor (CMOS) standard process. Post-layout simulations show 8 dB compression point improvement compared with the conventional CRLNA solution. The CRLNA draws a current of 650 μA from a 1.2 V supply. At 2.45 GHz, a power gain of 25.3 dB and a NF of 2.3 dB are achieved, while the IIP3 is À9 dBm.