Diffusion pipes in silicon NPN structures were investigated both by electrical measurements and by microsectioning. It was found that certain crystalline defects, specifically stacking faults and edge dislocations, can act as sites for the formation of such pipes. The presence of gold doping at these lattice defects greatly increases the incidence of pipes, apparently by offering a path of enhanced diffusivity for phosphorus from the emitter.

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Phosphorus diffusion into silicon has been explored near and above the solubility limit by radiochemical profiling and compared with crystal damage by x‐ray diffraction microscopy and Sirtl etch techniques. An apparent diffusion retardation has been found for very high source concentrations that results in a shallowed junction penetration for certain higher surface concentrations. The retardation phenomenon occurs over a narrow range of surface concentrations, within which diffused junctions are nonuniform, or ragged. This effect can be correlated with large amounts of crystal disorder inside the diffused area and dislocation loops outside at the peripheries. These outside loops have been found to degrade transistor gain.

Planar junctions in silicon can be degraded electrically by the growth of an oxide on the surface, particularly if the oxidation is carried out at low temperatures and at rapid rates. It is suggested here that the mechanism of degradation involves the formation of shallow dislocation loops due to dopant pile‐up at the surface as the oxide grows, followed by the precipitation of fast‐diffusing impurities about these defects. High‐temperature oxidation, especially at low growth rates, minimizes this problem.