Diffusion Pipes in Silicon NPN Structures

The emergence of crystalline silicon and silicon-based materials such as silicon-germanium as the premier materials and the personnel driving the integrated circuit ͑IC͒ microelectronics revolution will be reviewed. The major threshold events from the 1940s through the mid-1960s, presaging the onset of the large scale integration microelectronics era, will be highlighted. The major silicon material challenges such as dislocation-free single-crystal growth, plastic deformation, the point-defect dilemma, gettering, oxygen in silicon, carrier lifetime, and controlled point-defects in the silicon crystal during the evolution of silicon microelectronics from large scale integration through the very large scale integration era in the 1970s and the 1980s into the ultralarge scale integration era of the 1990s will then be reviewed. Opportunities in epitaxy, wafer cleaning, silicon-on-insulator, silicon-germanium, IC scaling and potential changes in device configuration and IC architecture in the evolution towards the 64 Gbit DRAM and 9 G transistor high-performance MPU logic era in 2016 ͑per the 2001 edition of the International Technology Roadmap for Semiconductors͒ will be discussed in the context of silicon-based microelectronics. The complementary role of compound semiconductors, nanoelectronics and the continuing initiative to obtain an optoelectronic system compatible with silicon will also be discussed. Finally, nonsilicon materials and device configurations will briefly be noted. © 2002 The Electrochemical Society. ͓DOI: 10.1149/1.1471893͔ All rights reserved.Available electronicallyApril 11, 2002. The computer and communications age has catapulted electronics to its current status as the dominant global industry. Indeed, we are in the midst of a revolution brought about by the availability of inexpensive information acquisition, manipulation, and distribution systems. Exploitation of electron and hole conduction in silicon has resulted in electronic memory and logic circuits such as the dynamic random access memory ͑DRAM͒ and microprocessor. Control of the interaction of photons with compound semiconductors has resulted in optical devices such as the laser and optical fiber networks. This revolution has been and will continue to be dependent on our ability to control electronic and photonic material processing techniques for the manufacture of useful devices, circuits and systems. The preparation and detailed processing sequence of a material from crystal growth through device and circuit fabrication determines the microstructure and, therefore, the electronic properties of the material and resulting device and circuit performance, yield, and reliability. Electronic materials include semiconductors, dielectrics, magnetics, piezoelectrics, optoelectronic materials, and optical fibers which may be utilized in crystalline, polycrystalline, or amorphous form. Materials are indeed the sine qua non of electronic and optical devices and circuits.An extensive list of relevant citations through 1997 is noted in Ref. ...

“…[112][113][114]120 The large number of variables noted above also contributed to the significant variability of carrier lifetime with the ''same'' dislocation density …”

Section: -114mentioning

confidence: 99%

Section: Plastic Deformation In Siliconmentioning

confidence: 99%

An Electronics Division Retrospective (1952-2002) and Future Opportunities in the Twenty-First Century

Huff¹

2002

“…Such pipes were found only under the phosphorus-diffused emitter areas and not in the remainder of the base area. This suggested a model that the pipes are a result of enhanced phosphorus diffusion along crystalline defects (4). The addition of gold increases the junction leakage suggesting that the precipitation of gold or other fast diffusers on the defects passing through the collector-base junction m a y also play a significant role (5).…”

Section: Diffusion Into Ion Implanted Surfacesmentioning

confidence: 99%

Adaption of Ion Implantation for Integrated Circuits

Prussin

Fern

1975

Ion implantation has become established as a useful process for MOS device manufacture. In this use the implantation process determines the positioning of the electrically active atoms. F u r t h e r processing consists of low temperature annealing whose primary function is to r e t u r n the implanted atoms to full electrical activity.For processing bipolar IC's, ion implantation is used primarily as a means of obtaining the uniform and reproducible deposition of electrically active impurity atoms. This is usually followed by high temperature heat-treatments which result in the redistribution of these deposited atoms. Such heat-treatments include the oxidation of the surface silicon as well as the indiffusion of additional chemical species. The interaction of these heat-treatments with the radiation defects introduced by the prior ion implantation has been shown to result in the generation of stacking faults and dislocation loops capable of affecting device performance (1).The interest in applying ion implantation as a deposition technique in the processing of bipolar integrated circuits stems from two sources, the inherent uniformity obtainable over an entire wafer surface and the reproducibility from wafer to wafer. This uniformity was evaluated by measuring the resistance of identical 10[~ resistors for 82 IC's which fitted over a 2 in. diameter wafer. The resistors were generated by implanting a fluence of 2.5 • 1013 p3~ cm-2 at an energy of 100 keV. The background was a p-well similar to that used in CMOS construction. Implantation was carried out at room temperature using commercially available equipment. The coefficient of variation, i.e., the standard deviation divided by the average resistor value was 1.0%. This uniformity is reflected in the uniformity of electrical parameters when ion implantation is used as a processing technique. Experimental StudyThis study was based on a specific IC design which had been successfully produced for several years by a triple diffusion technique for which a detailed performance record was available. The three chemical diffusions begin with an arsine collector deposition and drive. The base is formed by a BN deposition and a two-stage drive, first in wet N2 and then in dry N2. h PH3 emitter diffusion completes the diffusions. Test diodes permitted easy evaluation of aIt the following pn junctions: the n -p -collector-substrate junction. the p + n -base collector junction, the n + p + emitterbase junction and the n + p -emitter substrate junction.Experience indicated that the base deposition was the most critical diffusion operation and it was chosen for replacement with an implantation of 1.2 • 101~ B n cm -2 at 30 keV. The chemical emitter diffusion and other steps were maintained without change with one exception. Unless special precautions were taken with the base drive, heavy stacking fault concentrations resulted. These were found to correlate with excess leakage in the n + p + junctions. * Electrochemical Society Active Member. K e y words: t e r n a r y defects,...

“…It has been reported that RP silicon epitaxy has more advantage in characteristics of layer [autodoping, pattern shift, and uniformity of epitaxial layer, etc. (1)(2)(3)(4)(5)], than those of .atmospheric silicon epitaxy.…”

Section: Introductionmentioning

confidence: 99%

Pre‐ and Postepitaxial Gettering of Oxidation and Epitaxial Stacking Faults in Silicon

Chen

Silvestri

1981

Certain gettering treatments on the back sides of wafers have been found to be effective in reducing stacking faults in Si bulk wafers. In this study results are reported for various back side, front side, and combined gettering processes on wafers used to receive epitaxial films. Focus in this investigation was on the effectiveness of gettering measures in removing defects in epitaxial films. Results of POC18 diffusion, Ar ion implantation (I/I), abrasion, and SisN4 deposition as back-side treatments are reported as well as As I/I ,and boron diffusion front-side gettering effects. These treatments were employed either in the pre-or postepitaxial deposition mode. When used in the preepitaxial mode all of the back-side gettering techniques were found effective in reducing oxidation stacking faults (OSF) in epi films to levels of ~10 cm -2 as compared to nongettered levels of 100-10(}0 cm -2. In the post-opt application, Ar I/I was found to give moderate reduction of CSF defects. The back-side gettering techniques combined with front-side gettering used in a pre-epitaxial mode reduces epitaxial type stacking faults (SFepi) significantly and eliminates oxidation stacking faults (OSF) in the epitaxial films. Counts of SFepi were not reduced using the back-side gettering alone. The two front-side procedures were, however, found to reduce both the OSF and SFepi types. The epitaxia] films deposited on the As I/I surfaces showed a factor of ten reduction in SFepi defects and OSF types were reduced even more drastically. Boron diffusions in Si reduced OSF counts to nearly zero and SFepi faults by a factor of four over nongettered samples. Some effects of pre-epitaxial and postepitaxial oxidation treatments on stacking fault counts were also investigated. Results are also reported for effectiveness of stacking fault gettering relative to initial cleaning procedures used and stacking fault counts originating from substrates.