Aluminum bond pads on semiconductor chips play an important role in chips functionality and reliability. Bond pad peeling during wire bonding process results in yield reduction. The failure mechanisms of the peeling must be identified so that potential reliability problem of poor bond pad adhesion can be avoided. In this work, FIB, SEM, EDX, and AFM are used to identify the root causes of the peeling. The possible root causes are found to be the presence of an extra layer of thickness of 0.14 m and the poly-silicon surface roughness asperity due to prolonged BOE etching time.

Analytical thermomechanical models have been developed in order to calculate the thermally induced stresses in leadless solder interconnection systems. Two different analytical models are highlighted: the peripheral and area array thermomechanical model which describe the thermally induced stresses for two components connected to each other with a peripheral, respectively, area array of joints. The analytical models are based on structural mechanics and have the ability to characterize the nature and estimate the magnitude of the joint stresses. Using these models, structural design optimization of interconnection systems can be performed very quickly in order to reduce time consuming experiments and finite element simulations. It is found that the largest stresses in the solder joints of flip chip assemblies are at the top and bottom surface of the connection and that they are especially caused by bending moments subjected to the joints. Comparisons with finite element simulations have proved a good accuracy of the thermomechanical models.

The embedding of passive components such as resistors, capacitors and inductors within printed circuit boards (PCBs) is motivated, to a large extent, by the desire for increased miniaturisation of electronic goods. However, resistors and, to a lesser extent, inductors are heat generating devices, and the temperature developed within PCBs as the result of the operation of embedded passives is a significant aspect of the design of a multilayer PCB. Here we investigate, by simulation, temperature fields associated with operation of embedded resistors. It is shown that for board dimensions less than 2cm × 2cm temperatures achieved are higher than those associated with larger boards having identical structures and identical resistor heat generation. Detailed simulations are used to investigate the sensitivity of the temperature rises associated with embedded resistors to copper track coverage and to thermal coupling of the PCB to ambient on its upper and lower surfaces. The implications of these findings are discussed both in the context of the design of real PCBs and in the context of thermal simulation.

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