The capability of 90 nm CMOS technology for low-power RF front-ends is demonstrated using fully integrated low power low noise amplifiers. This paper presents a 5.25 GHz high linearity, high gain LNA design for a receiver architecture based on IEEE802.16a WMAN standard. First, we go through the standard in order to obtain the receiver specifications. Next we choose a suitable architecture for our receiver and simulate it using ADS cad tool to extract the specifications which are needed for the low noise amplifier. Finally we design our LNA based on the design method of Mr. D. K. Shaefer, also we improve the Greenhouse spiral inductor model and optimize it employing a random search algorithm named Simulated Annealing. The targeted frequency band is the unlicensed band UNII 5 GHz. The LNA achieves voltage gain of 24 dB, noise figure of 1.8 dB, the TIP3 of 7.5 dBm, and the reverse isolation is about -11. 6. Employing the 90 nm CMOS process, the LNA dissipates 1.75 mW using a 1.2 V supply voltage.

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A fully-integrated, dual-band, high gain, low noise amplifier designed for 802.16a WMAN standard is presented. The targeted frequency bands include un-licensed band UNII 5 GHz and licensed band Int'l 10 GHz. Our LNA design adopts wide band input matching scheme with adjustable load to achieve an area-efficient dual-band low noise amplifier. The LNA has also achieved the gain and noise figure of 16.1 dB and 3.6 dB at 5 GHz, and 15.7 dB and 7.6 dB at 10 GHz. Additionally, the input reflection coefficient is −7 dB and −16.5 dB, and the IIP 3 is 1.8 dBm and 1.1 dBm at 5 GHz and 10 GHz, respectively. Utilizing the 0.18 µm CMOS process, the LNA dissipates 14.4 mW using a 1.8 V supply voltage.

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