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A framework for designing a family of novel fast CRC generation algorithms is presented. Our algorithms can ideally read arbitrarily large amounts of data at a time, while optimizing their memory requirement to meet the constraints of specific computer architectures. In addition, our algorithms can be implemented in software using commodity processors instead of specialized parallel circuits. We use this framework to design two efficient algorithms that run in the popular Intel IA32 processor architecture. First,' algorithm doubles the performance of existing software-based, tabledriven CRC implementations based on the Sarwate [12] algorithm while using a 4K cache footprint. Second, a 'slicing-by-8' algorithm triples the performance of existing software-based CRC implementations while using an 8K cache footprint.

A Karatsuba-based 64b Galois field multiplier for ondie acceleration of public-key encryption is fabricated in 1.1V, 45nm CMOS and occupies 0.021mm 2 . 2-level Karatsuba design using interleaved 32b multipliers and folded datapath organization results in single-cycle latency at 3GHz operation with total power consumption of 74mW and 32% area reduction over conventional multipliers, resulting in 3.2x speedup of Diffie-Helman key exchange workloads.