A Systematic Approach to Building High Performance Software-Based CRC Generators

Abstract

A framework for designing a family of novel fast CRC generation algorithms is presented. Our algorithms can ideally read arbitrarily large amounts of data at a time, while optimizing their memory requirement to meet the constraints of specific computer architectures. In addition, our algorithms can be implemented in software using commodity processors instead of specialized parallel circuits. We use this framework to design two efficient algorithms that run in the popular Intel IA32 processor architecture. First,' algorithm doubles the performance of existing software-based, tabledriven CRC implementations based on the Sarwate [12] algorithm while using a 4K cache footprint. Second, a 'slicing-by-8' algorithm triples the performance of existing software-based CRC implementations while using an 8K cache footprint.

Efficient Data Integrity Verification Using CRC Based on HDFS in Cloud Storage

“…Kounavis and Berry [17] made some improvements in CRC algorithm of data integrity verification in cloud storage system. They improved CRC32 algorithm by seeking one single-bit table, and applied it in data processing platform Hadoop.…”

Parallel Computation of CRC Using Special Generator Polynomials

“…Kounavis, et al [10,15] proposed a frame fork for designing a family of parallel CRC algorithms. They showed that algorithms designed in this framework can reduce the memory required for calculating CRC and make it convenient for different computer system architectures.…”

Performance Increase of Error Control Operation on Data Transmission

“…According to this model the probability of error appearance with different multiplicity obeys the law of binomial distribution. In practice, for the transmission of the block, this means that the absence of errors is most probable and the probability of errors decreases with an increase in their multiplicity [5].…”

“…The parallel processing which is connected with the calculation of the CRC control code increases exponentially the architecture complexity depending on the number of simultaneously workable single bits of information in each data block B [5], [11].…”