In this paper, a novel voltage-boosting switched-capacitor multilevel inverter (SCMLI) capable of producing 19 voltage levels using a combination of only 10 switches, 4 diodes, 2 capacitors, and 2 DC sources has been proposed. The main features of the proposed topology are 1) utilization of a very low number of devices, 2) very low Total Standing Voltage (TSV) equal to 6.55 and 3) self-balance property of the capacitors' voltages. In order to provide the IGBTs of the circuit with the desired switching signals, the Nearest Level Control (NLC) method has been adopted. To clarify the benefits of the designed topology as to the total quantity of switches, DC sources, capacitors as well as the total standing voltage (TSV), and converter boosting, a thorough comparison has been carried out versus the recently published 19-level topologies. Also, for the purpose of performance evaluation and validation, the suggested topology has been tested against various loads through an experimental setup in the laboratory using TMS320F28379D DSP as the processor. The comparative, simulation, and experimental results all imply the superiority of the proposed topology against its predecessor counterparts.

Multilevel inverters are able to provide loads with voltages of high power quality using several DC sources, capacitors, switches, and diodes in their structures. However, the usage of the higher number of semiconductor devices (switches and diodes) and capacitors causes an increase in losses and costs and decreases their efficiency. Thus, lowering the number of switches and capacitors is a challenging issue in designing a multilevel inverter. In this paper, an asymmetrical multilevel inverter is proposed that produces 19-level output voltages. The circuit is composed of nine switches, six diodes, two capacitors, and two isolated DC sources. In comparison with other topologies, the most important advantage of the introduced 19-level topology is the usage of a lower number of switches and capacitors, which leads to a decrease in the number of gate drivers and the total volume of the system. During the charging process, capacitors never connect to each other in series, i.e., they are self-balancing and do not require the extra circuits. The proposed topology offers a total harmonic distortion (THD) of 7.4% in the output voltage, which is less than 8%, complying with the IEEE standards. The performance of the topology is validated under various load conditioning through an experimental setup in the laboratory.