SUMMARYIn this paper, we discuss the properties of new nanometer-size CMOS technologies being important for the circuit designer. Thereby we concentrate on analogue circuit design. In the literature, the gain reduction by the high output conductance of the transistors is discussed. In detail, we further describe gain reduction due to gate-leakage current. Finally, we present a design example of a fully differential operational amplifier in a 65 nm CMOS technology including results.

In this paper an advancement to compensate multistage operational amplifiers is presented. High-gain and highspeed operational amplifiers can be realized with this approach. One example of such a high-gain amplifier with a unity-gain frequency of 693 MHz and DC gain of 128.8dB is presented. The high-speed settling is mainly reached by dominant Miller compensation via 4 stages.

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