120nm CMOS OPAMP with 690 MHz f/sub T/ and 128 dB DC gain

Abstract

In this paper an advancement to compensate multistage operational amplifiers is presented. High-gain and highspeed operational amplifiers can be realized with this approach. One example of such a high-gain amplifier with a unity-gain frequency of 693 MHz and DC gain of 128.8dB is presented. The high-speed settling is mainly reached by dominant Miller compensation via 4 stages.

A rail-to-rail input stage with constant signal behavior in 0.12 μm CMOS

“…4. Separate CM feedback control for each stage also reinforces the robustness of a fully-balanced architecture [10]. Theoretically, for the structure with same type of differential amplification pair, only one pair of VLS is necessary at the input to entitle the rail-to-rail operation.…”

A low-voltage fully differential constant signal behavior rail-to-rail input stage in 0.12μm CMOS

“…Therefore the total effective bias current for transistors P1-P4 I in is kept as the same quantity in all three input CM conditions, and the bandwidth of the circuit is not restricted since no regulation with feedback is involved. Because a more reliable fully balanced architecture demands separate CM level regulation for each amplification stage [7], transistors N1 and N2 are controlled by a common-mode feedback (CMFB), which further regulates the signal behavior. The design in [4] employs only one pair of N-type VLS, which generates about -1.5dB voltage gain.…”