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High electric-field stresses were performed in polycrystalline silicon gate metal-oxide-semiconductor devices (capacitors and transistors) and defect generation was studied as a function of injecting electron densities for polarities of different high electric fields. This work was performed for different oxide thicknesses and technologies. The results show that the interface states were generated during electron injections from the silicon-substrate saturate. However, they present no saturation when created during electron injections from the gate. Our results show that the amount of this asymmetry depends strongly on oxide thickness, but it is oxide technology independent. A detailed analysis of our results allows us to suggest that a direct creation mechanism occurs when the injecting electrode is the gate. Anode-hole injection and trap-creation mechanisms are present under the two stress oxide field polarities, but their effects are reduced with decreasing oxide thickness.

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