This paper presents a new SAT-based CEC methodology for the verification of circuits with structural dependence.This methodology is based on circuit partitioning and special approaches for conflict clauses reuse, reducing highly the CEC problem complexity. Using this methodology it is possible to improve the overall verification time of similar and dissimilar circuits. For instance, for similar multiplier circuits it was possible to check equivalence up to 37 x 37 bit without any circuit topological information in nearly 40 minutes. For dissimilar circuits, the proposed methodology is able to check equivalence up to 24 x 24 bit in one hour overcoming the BDD-based approaches that using cutpoints cannot check beyond a 12 x 12 bit multiplier with reasonable time limit.

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This paper presents a new implication tool (Vimplic) which can be used to improve SAT-based Combinational Equivalence Checking. This tool quickly builds the implication graph of the miter circuit and traverse through it inferring implications among its nodes assignments. This set of implications and the miter circuit netlist are converted to Conjunctive Normal Form (CNF) and submitted to the SAT solver in order to prove equivalence between the two circuits of the miter. Using Vimplic we have been able to dramatically reduce the overall verification time of several circuits outperforming the state-ofthe-art techniques for CEC such as Berkmin561, NiVER, and C-SAT.

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