Improving SAT-based Combinational Equivalence Checking through circuit preprocessing

Abstract

This paper presents a new implication tool (Vimplic) which can be used to improve SAT-based Combinational Equivalence Checking. This tool quickly builds the implication graph of the miter circuit and traverse through it inferring implications among its nodes assignments. This set of implications and the miter circuit netlist are converted to Conjunctive Normal Form (CNF) and submitted to the SAT solver in order to prove equivalence between the two circuits of the miter. Using Vimplic we have been able to dramatically reduce the overall verification time of several circuits outperforming the state-ofthe-art techniques for CEC such as Berkmin561, NiVER, and C-SAT.

A global postsynthesis optimization method for combinational circuits

“…A common goal of the proposed techniques is to modify (preprocess) the input CNF instance in order to decrease the proving effort of the SAT solver. For example, a preprocessing tool which derives implications according to the computed implication graph is proposed in [14].…”

Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware

“…Although the results for LGSynth93 benchmarks are very encouraging, the SAT-based combinational equivalence checking can definitely perform unsatisfactory for some problem instances, for example for multipliers where the number of paths traversed by the SAT solver grows enormously with the increasing number of inputs. In order to improve performance of the SAT solver in this particular case, various techniques have been proposed to reduce the equivalence checking time [1,2]. The proposed method is assumed to be able to handle large-scale multipliers optimization if more advanced version of SAT solver is utilized.…”