Most power amplifiers (PA) for wireless power transfer (WPT) are based on single switch topologies (Class-E, F, Φ,). Single-switch topologies are easy to design and operate, but they are limited in power handling capability. Utilizing multi-switch topologies increases device utilization which improves power handling capability. In this paper a novel topology is introduced, which is referred as Class-PN. Class-PN is based on four switches, and is shown to have more than 6x higher power handling capability than Class-E. The topology consists of no resonating passive components, thus the same PA is operational at multiple switching frequencies. Series resonating load at output power of 135W and switching frequency of both 7MHz and 12MHz are shown at first to verify operation of Class-PN power amplifier. Finally, inductively coupled coils are used to transfer power wirelessly between the transmission and receiving coil. Wireless power delivered to the load at 6.15MHz of switching frequency is 400W, which was limited by the radio frequency (RF) load.

Power semiconductor devices are achieving high switching speed and high breakdown voltage. This improves inverter performance. But, as inverter improves, further challenge of dv/dt noise is generated that needs to be tackled by filter stage. Multilevel inverters can solve this challenge. But there are implementation complexity associated with multilevel topologies like requirement of multiple isolated DC source, complicated charging algorithm, dedicated sensing hardware. This paper presents a switch capacitor type converter topology enabling a DC-AC three level output. Joining multiple iterations of topology in daisychained configuration, the converter can achieve voltage gain with multilevel waveform. Requirement of a single DC supply, with inherent charge balancing capability on capacitor, the topology is well suited for low voltage renewable sources like photovoltaic (PV) or fuel cell. The paper presents design of high frequency commutation loop. Utilizing finite element analysis (FEA) tool ANSYS Electronics Desktop (Q3D) to extract PCB parasitics helps in eliminating prototyping cost and time. Designed inverter is then subjected to continuous load test where it shows improving performance with increasing inductive load.

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