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The objective of this study is to propose a new model for hiding text in an image. The proposed model use logical connective in propositional logic to calculate a new binary number of secret message. This model can produce a low computational complexity of steganography because of the simplicity of the proposed algorithm. Moreover, the using of simple operator but very efficient is expected to be able to hide high capacity of a secret message.

Real-time mission planning for Un-manned Aerial Vehicles (UAVs) is an important application that requires implementation of computer vision algorithms such as LocallyNormalized Cross Correlation (LNCC), with greater accuracy and throughput. Although the LNCC algorithm is the prime choice for image matching, its real time hardware implementation has proved to be a real challenge for hardware designers mainly due to its computational complexity. In this paper, a novel architecture for real time implementation of this scheme using Field Programmable Gate Array (FPGA) platform is proposed. In the proposed design, multiple computations are concurrently executed by incorporating parallelism in architectures through 4 FPGAs. The FPGAs are efficiently multiple synchronized along with efficient memory architecture to optimize match point results in minimum possible time. The exploration of the parallelism and reusability of results made it possible to meet timing constraints imposed in this research.

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