Heat dissipation from three-dimensional (3D) chip stacks can cause large thermal gradients due to the accumulation of dissipated heat and thermal interfaces from each integrated die. To reduce the overall thermal resistance and thereby the thermal gradients, this publication will provide an overview of several studies on the formation of sequential thermal underfills that result in percolation and quasi-areal thermal contacts between the filler particles in the composite material. The quasi-areal contacts are formed from nanoparticles self-assembled by capillary bridging, so-called necks. Thermal conductivities of up to 2.5 W/m K and 2.8 W/m K were demonstrated experimentally for the percolating and the neck-based underfills, respectively. This is a substantial improvement with respect to a state-of-the-art capillary thermal underfill (0.7 W/m K). Critical parameters in the formation of sequential thermal underfills will be discussed, such as the material choice and refinement, as well as the characteristics and limitations of the individual process steps. Guidelines are provided on dry versus wet filling of filler particles, the optimal bimodal nanosuspension formulation and matrix material feed, and the over-pressure cure to mitigate voids in the underfill during backfilling. Finally, the sequential filling process is successfully applied on microprocessor demonstrator modules, without any detectable sign of degradation after 1500 thermal cycles, as well as to a two-die chip stack. The morphology and performance of the novel underfills are further discussed, ranging from particle arrangements in the filler particle bed, to cracks formed in the necks. The thermal and mechanical performance is benchmarked with respect to the capillary thermal and mechanical underfills. Finally, the thermal improvements within a chip stack are discussed. An 8 - or 16-die chip stack can dissipate 46% and 65% more power with the optimized neck-based thermal underfill than with a state-of-the-artcapillary thermal underfill.

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The 3D-packaging technology makes it possible to stack the PCBs on top of each other and thus make full use of the third dimension. A unique space between the stacked PCB layers enables a reproducible technology without shortcuts or unconnected bumps. New applications in 3D-PDB-packages, called PCBMEMS can be realized with the combination of electric bumps and solder rings. The paper shows an fluidic cooled 11-PCB-layer with high power components. Water channels in the PCB-package dissipate the heat from the inside of the package to the environment. Heat dissipation is a bigger challenge for stacks of 3D-packages than for normal printed circuit boards (PCBs). This research paper investigates some design suggestions for a better heat dissipation. On the basis of this research paper, it becomes possible to choose the best suited PCB design. The experimental results were compared to thermal simulation results. The results of the measurements and FEM simulations show, how important it is to combine the electrical and geometrical functions of 3D packages with a thermally optimized PCB design. A better heat spreading and conduction in a 3D package makes the stack more reliable at higher power dissipation.

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The experimental observation of the actual thermo-mechanical weak points in microelectronics packages remains a big challenge. Recently, a stress sensing system has been developed by the publicly funded project that allows measuring the magnitudes and the distribution of the stresses induced in the silicon dies by thermo-mechanical loads. The paper reports investigations on industrial QFN packages of 6×6×1mm3 in size. The stress field has been recorded before and after soldering the component to the PCB as well as during thermal cycle and bending tests. Onset and evolution of internal damages have been detected by changes in the stress at the chip surface due to degradations of materials or interfaces within the course of the thermal cycling test. Applying 3-D x-ray computer tomography, the damages inside the packages have been validated at several stages during the test. All measurements are supplemented by finite element simulations based on calibrated models for in-depth analysis and for extrapolating the stress results to sites of the package that are not measured directly. The methodology of closely combining stress measurements and FE simulation presented in this paper has been able to validate the stress sensing system for tasks of comprehensive design and process characterization as well as for health monitoring. It allows achieving both, a substantial reduction in time-to-market and a high level of reliability under service conditions, as needed for future electronics and smart systems packages