The automatic generation of hardware implementations for a given algorithm is generally a difficult task, especially when data dependencies span across multiple iterations such as in iterative stencil loops (ISLs). In this paper, we introduce an automatic design flow to extract parallelism from an ISL algorithm and perform a design space exploration to identify its best FPGA hardware implementation, in terms of both area and throughput. Experimental results show that the proposed methodology generates hardware designs whose performance is comparable to the one of manuallyoptimized solutions, and orders of magnitude higher than the implementations generated by commercial high-level synthesis tools.

Abstract-In this paper, we face the problem of P-equivalence Boolean matching. We outline a formal framework that unifies some of the spectral and canonical form-based approaches to the problem.As a first major contribution, we show how these approaches are particular cases of a single generic algorithm, parametric with respect to a given linear transformation of the input function.As a second major contribution, we identify a linear transformation that can be used to significantly speed up Boolean matching with respect to the state of the art. Experimental results show that, on average, our approach is five times faster than the main competitor on 20-variables input functions, and scales better, allowing to match even larger components.

The problems of error simulation, error model evaluation, and test generation are faced considering the peculiar features of SystemC. In particular, error simulation are considered in the perspective of the transaction level modelling (TLM) capabilities of this emerging system level design language to obtain a coherent, environment for functional verification. The error simulation is accomplished without any modification of the native simulation engine, thus avoiding the problem of upgrading the error simulator together with the language simulation engine. Moreover, error modelling and error simulation tasks are orthogonalized in this approach. With the support of this environment, a test pattern generation algorithm for SystemC descriptions of systems made of interacting Finite State Machines (FSMs) is developed. The approach is based on the definition of the transitions, that represent ordered sets of statements executed within one clock cycle. Through different state sequence paths enumeration strategies, interesting behaviors of the system are obtained

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In this paper, we face the problem of P-equivalence Boolean matching. We outline a formal framework that unifies some of the canonical form-based approaches to the problem.As a first major contribution, we show how these approaches are particular cases of a single generic algorithm, parametric with respect to a given linear transformation of the input function.As a second major contribution, we identify a linear transformation that can be used to significantly speed up Boolean matching with respect to the state of the art. Experimental results show that, on average, our approach is five times faster than the main competitor on 20-variables input functions, and scales better, allowing to match even larger components.