The design for two high fill-factor CCD arrays for optical signal processing applications is described. The imaging registers have 1 024 x 1 024 and 51 2 x 51 2 pixels and achieve virtually 100% optical fill factor through the use of substrate thinning and back illumination. High frame-rate readout is obtained by the use of a dual storage register and multiple floating-diffusion output ports resulting in reduced readout frequency. On-chip correlated double sampling amplifiers are implemented to reduce the readout noise and simplify off-chip analog signal processing. Both chips include anti-blooming drain structures and ESD protection circuits.

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Back illuminated, 16-port 512 x 512 and 32-port 1024 x 1024 charge coupled device (CCD) imagers have been fabricated. The measured performance of the 512x 512 pixel chip is described, including data on quantum efficiency, dynamic range, dark current, frame rates, uniformity, contrast transfer function, and onchip correlated double-sampling (CDS) amplifier noise.We have previously reported on these designs [1]. The CCD arrays are designed with a unique combination of parameters optimized for applications requiring high resolution combined with high frame rates and wide dynamic range. The imaging registers achieve 100% optical fill factor and high quantum efficiency through the use of substrate thinning and back-side illumination. The high frame-rate readout is obtained by the use of a dual storage register and multiple floating-diffusion output ports which reduce the 512 x 512 array readout frequency to 15 MHz for 800 frame per second operation. On-chip CDS amplifiers are included in each output port to reduce the readout noise and simplify off-chip analog signal processing. Both designs include a buried anti-blooming drain structure and electro static discharge (ESD) protection.