We report a strong Kondo effect (Kondo temperature ϳ4 K) at high magnetic field in a selective area growth semiconductor quantum dot. The Kondo effect is ascribed to a singlet-triplet transition in the ground state of the dot. At the transition, the low-temperature conductance approaches the unitary limit. Away from the transition, for low bias voltages and temperatures, the conductance is sharply reduced. The observed behavior is compared to predictions for a two-stage Kondo effect in quantum dots coupled to single-channel leads. DOI: 10.1103/PhysRevLett.88.126803 PACS numbers: 73.23.Hk, 72.15.Qm The observation of the Kondo effect in quantum dots [1 -3] has led to an increased experimental and theoretical interest in this many-body phenomenon. Unlike the conventional case of bulk metals containing magnetic impurities [4], quantum dots [5] offer the possibility to study the Kondo effect at the level of a single artificial magnetic impurity [6], allowing one to tune different parameters. Experiments on quantum dots have also revealed novel Kondo phenomena that have no analog in bulk-metal systems. In particular, multilevel Kondo effects have been studied both theoretically [7][8][9][10][11][12] and experimentally [13][14][15] that differ substantially from the ordinary case of a spin-1͞2 Anderson impurity.In this Letter, we present results on a strong Kondo effect in a lateral quantum dot at high magnetic field. We associate the Kondo effect with a magnetically induced crossing between a spin-singlet and a spin-triplet ground state [9 -14]. In contrast to the results for a vertical semiconductor quantum dot [13] and for a carbon nanotube dot [14], we find a sharp reduction of the conductance at low bias voltage, V SD , and temperature, T. We ascribe the different behavior to the number of channels in the leads which couple to the states in the dot. In lateral dots, tunnel barriers are obtained by successively pinching off the propagating channels. Coulomb blockade develops when the last channel is nearly pinched off. Therefore, only one channel in each lead is coupled to the dot [16]. In vertical dots, however, the tunnel barrier characteristics are determined by the growth parameters, i.e., by the thickness of the different semiconductor materials forming the heterostructure and their relative conduction band offsets. In this case, more than one conducting channel can effectively couple to the dot states. The same is true for carbon nanotubes connected to metal leads. Our results, in combination with previous findings [13,14], show that screening of higher spin states (S $ 1͒ depends strongly on the number of channels coupled to the (artificial) magnetic impurity. Comparison is made to recent theoretical studies on quantum dots in Refs. [16,17], which are partly inspired by the experimental work presented here.Our device (Figs. 1a and 1b) consists of a lateral quantum dot [18] with a nominal diameter ϳ300 nm that is further decreased by application of a negative voltage to the top gate electrode (Fig. 1a)....

Artificial two-dimensional semiconductor Kagome lattice structures formed by quantum wires can show ferromagnetism when the flatband is half filled, even though it does not have any magnetic elements. Experimental realization of such a Kagome lattice structure is reported. The structure, with different pattern periods, was formed with GaAs quantum wires by selective area metalorganic vapor phase epitaxy on GaAs ͑111͒B substrates. To overcome the lateral overgrowth and to improve the shape of smaller period pattern, flow rate modulation epitaxy was employed and a GaAs Kagome lattice structure with 1 m period was effectively grown.

We describe a method for fabricating GaAs dot arrays and dot-wire coupled structures having periodic nanofacets which uses selective area metalorganic vapor phase epitaxy. First, a thin GaAs buffer layer and an AlGaAs layer are grown on a masked substrate having wirelike openings with periodic width modulation. The width of AlGaAs wirelike structure is naturally squeezed by the periodic combination of nanofacets, and its top ͑001͒ surface is partially isolated by a self-limited region. Next, an AlGaAs/GaAs quantum well structure is fabricated on the substrate to form dots on the narrower top terraces, wires on the wider terraces, and ridge wires in the self-limited region. Cathodoluminescence images clearly showed dot arrays and dot-wire coupled structures were formed using this method. A single electron transistor with the same structure was also fabricated, and clear Coulomb blockade oscillation was observed. We also describe single electron tunneling devices with these dot arrays and dot-wire coupled structures.

We experimentally demonstrated single-electron operations of an AND/NAND logic circuit based on a self-organized GaAs quantum-dot ͑QD͒ network fabricated by applying a selective-area metalorganic vapor-phase epitaxy technique. Single-electron logic operations using four cooperating single-electron tunneling ͑SET͒ transistors has been tested. This logic circuit has an architecture based on a binary decision diagram ͑BDD͒ using a Coulomb blockade ͑CB͒ in GaAs QDs, which is a representation of digital logic functions using directed graphs. BDD node devices consisting of two SET transistors achieved a two-way path switching operation in single-electron mode due to the CB effects which appeared complementarily in the two SET transistors at 1.9 K. We also demonstrated an AND/NAND operation in a logic circuit by integrating two BDD nodes. Single-electron logic circuits have received substantial attention because they have a low power consumption and a high-density integration, which enables adding a new function to present devices. 1,2 This is because single-electron tunneling ͑SET͒ transistors can control the exact number of electrons in a nanoscale island via Coulomb blockade ͑CB͒ effects. To date, SET circuits using complementary-metaloxide-semiconductor ͑CMOS͒-type logic architectures have been developed. [3][4][5][6] However, the practical problems of highdensity integration, such as small gain and the unilateral nature of the devices, impede replacing CMOS logic circuits of current large-scale integrated circuits ͑LSIs͒ in conventional architecture. Thus, an architecture based on binary decision diagram ͑BDD͒ is proposed for SE-logic system applications to overcome these shortcomings. 7,8 In this architecture, the key device as a unit element of the circuit is called a BDD node device, which works as a path switch of SE transport between two branches using CB, 9 and the function of any complicated logic can be realized by the combination of the node devices.Because the BDD logic architecture is based on the graphical representation of the logic, it is feasible if the network-like structure of SET transistors arrays is realized. 10 In this letter, we report on the fabrication and experimental operation of SET logic circuits based on network of GaAs quantum dot ͑QD͒ and quantum wires ͑QWRs͒. Arrays of SET transistors utilizing a QD are fabricated by using selective-area metalorganic vapor-phase epitaxy ͑SA-MOVPE͒ on partially masked GaAs substrates. 3,11,12 Based on these nanostructures, SE BDD logic circuits are constructed by integrating four SET transistors. Figure 1͑a͒ shows an array of SET transistors grown by SA-MOVPE. The unit cell of the array is the region enclosed by the white box and is schematically shown in Fig. 1͑b͒. It consists of four SET transistor structures. As we reported in previous papers, 12,13 each SET transistor structure, consisting of a QD, QWRs, and tunneling barriers, indicated by the white circle in the figure, can be fabricated by SA-MOVPE growth on partially masked GaAs ͑001͒ substra...

GaAs single electron transistors (SETs) are successfully fabricated using selectively grown GaAs/AlGaAs modulation doped structures by metalorganic vapor phase epitaxy (MOVPE) on (001) GaAs masked substrates. SET shows clear Coulomb oscillations and Coulomb gaps modulated by gate voltage. GaAs single electron tunneling inverter circuits having a SET and a variable load resistance are also formed. The operation of a resistance-load inverter circuit is confirmed at 1.9 K from the transport properties of this SET and input-output characteristics.