Low-temperature photoluminescence (PL) spectroscopy is a very sensitive tool to investigate the presence of dislocations in Si. The main dislocation-related bands (D1-D4) have been attributed to a wide range of causes, either intrinsic properties of the dislocation or impurity related. PL is a competitive recombination process and the non-radiative processes need to be measured to understand the overall effect of impurities. PL spectroscopy samples a large volume in comparison to the dislocation itself and therefore gives an average effect. High-resolution room-temperature PL mapping (SiPHER) has been used to detect defects in both Si and SiGe wafers. Whole-wafer PL maps reveal the presence of slip on 300 mm Si wafers. Comparison studies with defect etching show that there is a one-to-one correlation between defects detected in the PL micro-scans and those revealed by defect etching. Whole-wafer mapping has revealed a number of different defect types in SiGe epilayers. The ability to record whole-wafer PL maps facilitates the rapid identification of inhomogeneities and defects. High-resolution PL micro-maps showed the defect area to contain a high density of misfit dislocations, and the nucleation site has strong non-radiative recombination. One common defect type was analysed using plan view transmission electron microscopy (TEM) and optical microscopy; these results revealed the presence of a high density of defect loops and stacking faults consistent with the high recombination rate at the defect site.

This study investigates an advanced copper (Cu) chemical displacement technique (CDT) with varying the chemical displacement time for fabricating Cu/SiO2-stacked resistive random-access memory (ReRAM). Compared with other Cu deposition methods, this CDT easily controls the interface of the Cu-insulator, the switching layer thickness, and the immunity of the Cu etching process, assisting the 1-transistor-1-ReRAM (1T-1R) structure and system-on-chip integration. The modulated shape of the Cu-SiO2 interface and the thickness of the SiO2 layer obtained by CDT-based Cu deposition on SiO2 were confirmed by scanning electron microscopy and atomic force microscopy. The CDT-fabricated Cu/SiO2-stacked ReRAM exhibited lower operation voltages and more stable data retention characteristics than the control Cu/SiO2-stacked sample. As the Cu CDT processing time increased, the forming and set voltages of the CDT-fabricated Cu/SiO2-stacked ReRAM decreased. Conversely, decreasing the processing time reduced the on-state current and reset voltage while increasing the endurance switching cycle time. Therefore, the switching characteristics were easily modulated by Cu CDT, yielding a high performance electrochemical metallization (ECM)-type ReRAM.

Nanoscale‐crossbar electrochemical‐metallization (ECM) type resistive‐switching random access memory (ReRAM) is considered promising candidates for next‐generation non‐volatile memory. However, performing nanoscale patterning with traditional Cu‐based ECM ReRAM is quite challenging, because Cu is difficult to control and pattern using lithography and etching. In this study, a nanoscale Cu‐based ReRAM with a Si3N4–SiO2 bi‐layer was fabricated successfully through a novel Cu chemical displacement technique (Cu‐CDT). Compared with other conventional Cu deposition techniques, the Cu‐CDT exhibits numerous advantages including simplicity, low‐temperature fabrication, low cost, and high displacement selectivity between poly‐Si and the Si3N4–SiO2 bi‐layer. Moreover, the developed nanoscale‐crossbar Cu‐CDT ReRAM device demonstrated stable switching and remarkable high‐temperature data retention. Therefore, the Cu‐CDT is an effective approach for overcoming Cu etching and patterning limitations.

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