The growth process and the microstructure of very thin W films (80–500 Å) deposited by rf sputtering on SiO2 and Si substrates have been observed by transmission electron microscopy (TEM). The resistivity and stress in these films have been related to the film microstructure, composition, and to the deposition conditions (substrate bias and rf deposition power). Thin W films deposited on silicon dioxide substrates under zero or positive bias have been found to grow in two distinct growth stages. Stage I corresponds to the formation of a thin continuous film (80–100 Å thick) of β-W. The β-W phase has the A-15 crystal structure and has been identified as a faulted W3W compound. A small grain size (50–100 Å) is characteristic of the β-W film. Stage II corresponds to the transformation of the β-W film into a pure α-W film with the bcc crystal structure. This thermally activated phase transformation takes place in the temperature range 100–200 °C. It is characterized by the growth of α-W nuclei until complete coalescence of the α-W islands; the resulting α-W film consists of large grains (1500–2500 Å) which are free of dislocations. The end of stage II occurs for a critical film thickness tc beyond which the film is a continuous α-W film. The value of tc is controlled by the rf deposition power and the substrate temperature. On the other hand, films deposited on negatively biased substrates do not contain the β-W phase. These films consist of large α-W grains (1500–2000 Å) with a high dislocation density. The resistivity of thin W films deposited under zero or positive bias is controlled by the amount of β-W present in the film. The pure β-W films have a high resistivity (100–300 μΩ cm); after the complete transformation β-W→α-W the large resistivity (30–40 μΩ cm) of these films is attributed to scattering by impurities. In particular, the lower resistivity of W films deposited under negative bias is related to their lower oxygen content. The sign and magnitude of the stress in these films are also controlled by the film microstructure, It is found that the stress in the films containing the β-W phase is always tensile with a σ of (6–12) × 109 dyn/cm2. The films consisting of α-W are always compressively stressed in the range (2–12) × 109 dyn/cm2.
A study of the formation of epitaxial stacking faults in 2 in. diameter, dislocation‐free (111) silicon wafers used in the fabrication of standard buried collector transistors has been made. The nucleation sites for the epitaxial faults are introduced during the initial oxidation of the wafer and are correlated with the presence of a high density of shallow, flat‐bottomed, saucer‐shaped etch pits. The saucer pits are selectively annihilated in the diffused or implanted regions during the fabrication of the Sb‐doped buried collectors. For the ion‐implanted process the annihilation of saucer pits extends laterally from 50 to 100 μm beyond the boundaries of the collectors. Following epitaxial growth, epitaxial stacking faults, at a density of 104 cm−2, are only found in those nonburied layer regions which have a saucer pit density of 106–107 cm−2 before epitaxy. Therefore, epi stacking faults are not found in ion‐implanted material with a separation between buried collectors of 100 μm or less. Most 3 in. diameter, and the central regions of 2 in. diameter wafers do not have saucer pits or epi stacking faults. This is attributed to anin situ gettering of nucleation sites by
SiO2
precipitates, which are known to form in wafers, or regions of wafers, with a high initial oxygen concentration. Additional procedures for deliberately suppressing or gettering the nucleation sites are presented. These include deliberate abrasion, deposition of strained
Si3N4
layers, introduction of misfit dislocations, and the use of an Sb ion implant, which are performed on the back side of wafers before the initial masking oxidation.
In the present paper a preoxidation gettering procedure (called POGO) is described which prevents the formation and/or activation of stacking fault nucleation sites during oxidation. In this way the stacking faults and their possible device degrading influences are eliminated at the start of a processing schedule. In addition, the gettering medium is retained through all subsequent high temperature processing, thereby continuing to suppress the formation of stacking faults. The gettering of the nucleation sites, whether they be process induced, such as impurity precipitation, or native to the original crystal growth, such as vacancies or impurities, is achieved by the controlled introduction of interfacial misfit dislocations on the back side of the wafer. The dislocations interact with the stacking fault nucleation sites such that the nuclei diffuse from the active device side of the wafer to the line defects which are confined to within a few microns of the back surface.
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