The Identification, Annihilation, and Suppression of Nucleation Sites Responsible for Silicon Epitaxial Stacking Faults

Abstract

A study of the formation of epitaxial stacking faults in 2 in. diameter, dislocation‐free (111) silicon wafers used in the fabrication of standard buried collector transistors has been made. The nucleation sites for the epitaxial faults are introduced during the initial oxidation of the wafer and are correlated with the presence of a high density of shallow, flat‐bottomed, saucer‐shaped etch pits. The saucer pits are selectively annihilated in the diffused or implanted regions during the fabrication of the Sb‐doped buried collectors. For the ion‐implanted process the annihilation of saucer pits extends laterally from 50 to 100 μm beyond the boundaries of the collectors. Following epitaxial growth, epitaxial stacking faults, at a density of 104 cm−2, are only found in those nonburied layer regions which have a saucer pit density of 106–107 cm−2 before epitaxy. Therefore, epi stacking faults are not found in ion‐implanted material with a separation between buried collectors of 100 μm or less. Most 3 in. diameter, and the central regions of 2 in. diameter wafers do not have saucer pits or epi stacking faults. This is attributed to anin situ gettering of nucleation sites by SiO2 precipitates, which are known to form in wafers, or regions of wafers, with a high initial oxygen concentration. Additional procedures for deliberately suppressing or gettering the nucleation sites are presented. These include deliberate abrasion, deposition of strained Si3N4 layers, introduction of misfit dislocations, and the use of an Sb ion implant, which are performed on the back side of wafers before the initial masking oxidation.

Transmission electron microscopy investigation of the micro-defects in Czochralski silicon

“…Obviously, the formation of DZ is sensitive to initial oxygen concentration, thermal history and carbon concentration, etc. Thus, it is conceivable that the conventional high-low-high method having a high thermal budget will exert an adverse impact on the manufacture of devices, such as the redistribution of impurities, altering shallow junction structure and so on, thus degrading the performance of the devices [1,3,4]. Recently, Falster et al has proposed the Magic Denuded Zone (MDZ) concept, in which the formation of DZ is only dependent on RTA pre-annealing [5,6] while independent of all the parameters mentioned above, which makes it easy to form reproducible and reliable DZ [7].…”

Denuded Zones in Czochralski Silicon Wafers

“…The experimental results from Yue and Ruiz (1979), Rozgonyi, Deysher and Pearce (1976), and Craven et al (1981) showed that denuded zones could also form in an oxidation ambient during preannealing. Yue et al (1977) indicated that out-diffusion could occur in a steam or dry C>2 ambient when the temperature was about 1000°C.…”

Influence of nickel precipitation on the formation of denuded zone in Czochralski silicon

“…It has been widely accepted the nickel precipitation temperature in Cz silicon is above 800 • C, and nickel mainly occupied interstitial sites or formed different types of nickel complexes if the annealing temperature was lower than 800 • C, such as 750 • C [14,15,25]. For the interstitial oxygen atoms in Cz Si, it is well known that 750 • C is the optimum temperature for oxide precipitates to nucleate [1,2,26], which hints that the oxygen precipitate nuclei can act as the sink to absorb part of Ni I due to the lower barrier. It should be pointed out here that the oxygen precipitate nuclei only exist in the bulk while not in the region just below the surface.…”

“…Thus, the removal of the transition metals by the oxygen precipitates and related defects, back-side damage, phosphorous diffusion and implantation-induced damage, etc., from device active regions has proven indispensable to improve the yield of IC devices. It is well recognized that 3d-transition metals precipitation process is strongly dependent on the doping type and concentration, cooling rates, intrinsic point defects and induced defects in bulk silicon [1][2][3][4][5]. Recently, nickel gettering has been paid more attention because nickel contamination degrade the gate oxide integrity, which is comparable to the breakdown effects due to iron contamination [3].…”