Abstract-Dynamic power management (DPM) is a design methodology for dynamically reconfiguring systems to provide the requested services and performance levels with a minimum number of active components or a minimum load on such components. DPM encompasses a set of techniques that achieves energy-efficient computation by selectively turning off (or reducing the performance of) system components when they are idle (or partially unexploited).In this paper, we survey several approaches to system-level dynamic power management. We first describe how systems employ power-manageable components and how the use of dynamic reconfiguration can impact the overall power consumption. We then analyze DPM implementation issues in electronic systems, and we survey recent initiatives in standardizing the hardware/software interface to enable software-controlled power management of hardware components.

Energy consumption of electronic devices has become a serious concern in recent years. Power management (PM) algorithms aim at reducing energy consumption at the system-level by selectively placing components into low-power states. Formerly, two classes of heuristic algorithms have been proposed for power management: timeout and predictive. Later, a category of algorithms based on stochastic control was proposed for power management. These algorithms guarantee optimal results as long as the system that is power managed can be modeled well with exponential distributions. We show that there is a large mismatch between measurements and simulation results if the exponential distribution is used to model all user request arrivals. We develop two new approaches that better model system behavior for general user request distributions. Our approaches are event driven and give optimal results verified by measurements. The first approach we present is based on renewal theory. This model assumes that the decision to transition to low power state can be made in only one state. Another method we developed is based on the Time-Indexed Semi-Markov Decision Process model (TISMDP). This model has wider applicability because it assumes that a decision to transition into a lower-power state can be made upon each event occurrence from any number of states. This model allows for transitions into low power states from any state, but it is also more complex than our other approach. It is important to note that the results obtained by renewal model are guaranteed to match results obtained by TISMDP model, as both approaches give globally optimal solutions. We implemented our power management algorithms on two different classes of devices: two different hard disks and client-server WLAN systems such as the SmartBadge [19] or a laptop. The measurement results show power savings ranging from a factor of 1¡ 7 up to 5¡ 0 with insignificant variation in performance.

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IT IS OUR PLEASURE TO INTRODUCE this special issue on networks on chips (NoCs). Large, complex multiprocessor-based SoC platforms are already well into existence, and, according to common expectations and technology roadmaps, the emergence of billion-transistor chips is just around the corner. The complexity of such systems calls for a serious revisiting of several onchip communication issues. In this special issue, we focus on an emerging paradigm that effectively addresses and presumably can overcome the many on-chip interconnection and communication challenges that already exist in today's chips or will likely occur in future chips. This new paradigm is commonly known as the network-on-chip paradigm. The articles featured in this issue come from outstanding experts from around the world, from both industry and academia. Together, the articles reveal and discuss a wide range of issues specifically pertinent to NoCs. They also provide perspective based on actual practice, as well as more-speculative perspectives. To achieve a good degree of self-containment in this issue, we've included a more tutorial/survey type of article to lead a group of four specific and detailed articles.The NoC paradigm is one, if not the only one, fit to enable the integration of an exceedingly large number of computational, logic, and storage blocks in a single chip (otherwise known as a SoC). Notwithstanding this school of thought, the adoption and deployment of NoCs face important issues relating to design and test methodologies and automation tools. In many cases, these issues remain unresolved. On-chip interconnection networkSet-top boxes, wireless base stations, high-definition TV, and mobile handsets are just a few applications that have arisen because of multiprocessor SoCs. With such chips, the constraints for performance, power consumption, reliability, error tolerance and recovery, cost, and so forth can be extremely severe. One design characteristic that lies at the core of all these critical specifications is the on-chip interconnection network. Many experts advocate regularity in such networks as opposed to continuing with the more traditional ad hoc networks that have evolved over the past decades of IC design. Hence, much research and practical interest has recently focused on regular networks implemented on chip, often influenced by the parallel-computing field. When integrated on chip in the form of micronetworks, these regular networks are referred to as NoCs.Effective on-chip implementation of networkbased interconnect paradigms requires developing and deploying a whole new set of infrastructure IPs and supporting tools and methodologies. For example, NoCs require switches and router blocks, as well as corresponding communication formats and protocols. The design complexity of conventional SoCs is already soaring, so it's understandable that the development of SoCs based on nontraditional models might at first appear overwhelming and hence unnecessary or undesirable. However, when the specifications of these system...

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