The BIST technique for logic circuits improves access to internal signals from primary input/outputs. This paper presents programmable logic BIST architecture for testing ASIC chips. The scheme is based on STUMPS [6] (Self Test Using MISR [4, 6] and Parallel Shift register) architecture which uses an on-chip circuitry to generate the test patterns and analyze the responses with no or little help from an ATE. External operations are required only to initialize the Built-in tests and to check the test results. The system is synthesized in Xilinx ISE 10.1 to get the frequency of operation and in DesignCompiler for timing Analysis. Multi Voltage design for power reduction is successfully implemented.

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System on Chip (SoC) design is becoming challenging due to its complexity and the necessity of Intellectual Properties (IP) reuse to shorten the design time. An efficient bus protocol for the core communication between IP block is OCP. Open Core Protocol (OCP) defines the only nonproprietary, openly licensed, core centric protocol with highperformance, bus-independent interface between IP cores that reduces design time, design risk, and manufacturing costs and promote IP core reusability for SOC designs. Bus Bridge interconnects other bus standard to OCP. I2C is a simple bidirectional two wire bus for efficient inter IC control .This paper focus on the design and implementation of Bus Bridge using OCP master and I2C slave protocol. The power reduction using Multi voltage design is the important feature of the paper. The developed FSM's for OCP and I2C were implemented in VHDL and the Synthesis is done using Xilinx ISE 10.1 and Synopsys ASIC synthesis tool design compiler.

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