32-bit reconfigurable logic-BIST design using Verilog for ASIC chips

Bhakthavatchalu, Ramesh; Deepthy, G R; Mallia, S Sreenivasa; Krishnan, Arun K.; Sruthi, B

doi:10.1109/raics.2011.6069340

Cited by 6 publications

(2 citation statements)

References 3 publications

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“…It focuses on at-speed testing, power efficiency through multi-voltage design, and area cost reduction, with successful tool implementation demonstrated in Xilinx ISE and Design Compiler. These studies underscore a shift towards more efficient, flexible, and power-conserving testing methodologies in semiconductor design [17][18][19][20].…”

Section: Literature Reviewmentioning

confidence: 99%

Designing Power-Efficient BIST Architecture: Leveraging Reversible Logic for Scalable Digital Systems

Ramakrishna S , Rajashekhar B Shettar

2024

jes

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This paper presents a novel approach to optimizing power usage in scalable Built-In Self-Test (BIST) controllers. While BIST mechanisms are crucial for maintaining the reliability of digital circuits, they can be excessively power-hungry during testing phases, particularly in applications where energy consumption is a concern. We propose an innovative architecture incorporating reversible logic gates and circuits to overcome this challenge. Reversible logic is renowned for its low power consumption as it retains information. By integrating reversible logic into our architecture, we can significantly reduce power usage during test cycles, making it an ideal solution for scalable systems ranging from 8 to 32 bits. Our trials showed substantial power savings compared to traditional BIST approaches without sacrificing test coverage or efficiency. Our research provides new opportunities to develop energy-efficient testing methods for digital circuits, contributing to broader efforts in sustainable electronics design.

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Section: Literature Reviewmentioning

confidence: 99%

Designing Power-Efficient BIST Architecture: Leveraging Reversible Logic for Scalable Digital Systems

Ramakrishna S , Rajashekhar B Shettar

2024

jes

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“…It supply fault coverage of 90 to 95 % or more, using only a clock and a "test-mode" signal as inputs. Outputs are simplified since a good/bad test can be simplified to a single output signal [1] LBIST is one that can be used for several applications to Design For Test (DFT). It is one of legion types of built-in self-test.…”

Section: Introductionmentioning

confidence: 99%

Design and Testing Parallel Prefix Adders using Reconfigurable LFSR in FPGA

Munnur¹

2019

IJRASET

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The main criteria of this paper is to design Reconfigurable Linear Feedback Shift Register (LFSR) for very large scale integration(VLSI) of Integrated Circuit(IC) testing .Comparability to the Automatic Test Equipment(ATE) the Logic Built In Self Test(LBIST) has take into popularity. This logic built which helps in built testing with the help of additional hardware construction indoors the circuit. Thus doesn't contains the test pattern but they generate by the testing circuits. By this can out down the testing cost substantially. LFSR is mostly used as a test pattern generate for IC testing. To improve the fault coverage of IC testing in logic BIST using Reconfigurable LFSR. It is configurable to generate the maximum length of the pattern depending on the feedback polynomial that provide as per requirement. In this paper, the proposed reconfigurable LFSR of four structural represented in modular, standard, hybrid and complete LFSR is simulated in different sizes (8,16,32,64) in Xilinx Spartan 3E with an application of Parallel Prefix Adder (konge stone) of 16-bit.This simulation results shows the increasing of

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