Presently two major limiting factors are hindering the failure analysis (FA) development during the semiconductor manufacturing process and technology improvement: (1) Impossibility of manual polishing on the edge dies due to the amenability of layer peeling off; (2) Abundant demand of multi-locations FA, especially focusing different levels of layers simultaneously. Aiming at resolving these limitations, here we demonstrate two unique high precision polishing methods by using focused ion beam (FIB) technique. One is the vertical top down chemical etching at the aimed location; the other one is the planar top down slicing. Using the FIB for delayering not only solves these problems mentioned above, but also offers significant advantages over physical planar polishing methods such as: (1) having a better control of the delayering progress, (2) enabling precisely milling at a region of interest, (3) providing the prevention of over-delayering and (4) possessing capability to capture images at the region of interest simultaneously and cut into the die directly to expose the exact failure without damaging other sections of the specimen.

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With technology scaling of semiconductor devices and further growth of the integrated circuit (IC) design and function complexity, it is necessary to increase the number of transistors in IC’s chip, layer stacks, and process steps. The last few metal layers of Back End Of Line (BEOL) are usually very thick metal lines (>4μm thickness) and protected with hard Silicon Dioxide (SiO2) material that is formed from (TetraEthyl OrthoSilicate) TEOS as Inter-Metal Dielectric (IMD). In order to perform physical failure analysis (PFA) on the logic or memory, the top thick metal layers must be removed. It is time-consuming to deprocess those thick metal and IMD layers using conventional PFA workflows. In this paper, the Fast Laser Deprocessing Technique (FLDT) is proposed to remove the BEOL thick and stubborn metal layers for memory PFA. The proposed FLDT is a cost-effective and quick way to deprocess a sample for defect identification in PFA.

With the scaling of semiconductor devices to nanometer range, ensuring surface uniformity over a large area while performing top down physical delayering has become a greater challenge. In this paper, the application of laser deprocessing technique (LDT) to achieve better surface uniformity as well as for fast deprocessing of sample for defect identification in nanoscale devices are discussed. The proposed laser deprocess technique is a cost-effective and quick way to deprocess sample for defect identification and Transmission Electron Microscopy (TEM) analysis.