The continuous scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) led to the considerable impact in the analog-digital mixed signal integrated circuit design for system-on-chips (SoCs) application. SoCs trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design based on existing CMOS technology. In this paper, we have designed and analyzed a 3-bit high speed, low-voltage and low-power flash ADC at 32nm CNFET technology for SoC applications. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded carbon nanotube field effect transistor (CNFET) inverters as a comparator. The TIQ technique proposed has been developed for better implementation in SoC applications. The performance of the proposed ADC is studied using two different types of encoders such as ROM and Fat tree encoders. The proposed ADCs circuits are simulated using Synopsys HSPICE with standard 32nm CNFET model at 0.9 input supply voltage. The simulation results show that the proposed 3 bit TIQ technique based flash ADC with fat tree encoder operates up to 8 giga samples per second (GSPS) with 35.88µW power consumption. From the simulation results, we observed that the proposed TIQ flash ADC achieves high speed, small size, low power consumption, and low voltage operation compared to other low power CMOS technology based flash ADCs. The proposed method is sensitive to process, temperature and power supply voltage variations and their impact on the ADC performance is also investigated.

brought recently. The table below shows the applications used so far by the implementation ofBIO-MEMS based sensors.

The dynamic power dissipation is the dominant source of power dissipation in CMOS circuits. It is directly related to the number of signal transitions and glitches. The glitches occupy a considerable amount of power of the total power dissipation in CMOS circuits. This paper presents a survey of the different techniques used for decreasing the dynamic power by reduction of glitches. The advantages and limitations of these techniques are also discussed.Glitches, CMOS circuits, low power, path balancing, gate sizing.

ABSTRACT:This paper discuss the various types of BioInstrumentaion amplifier designs for the amplification of bio signals fabricated using the CMOS technologies.The Bioamplifiers play an important role in biomedical implant devices like hearing aids ,pacemaker etc.Those ampliefiers are surveyed based on different techniques used for circuit design and fabrication methodologies. The different techniques such as level shifting, cascading, cascading and multistage amplifiers have been used to reduce the power consumption and also to achieve high gain and CMRR,which are discussed in this work.The comparison for existing bio amplifers in terms of CMRR,voltage gain ,noise level and bandwith are carried out in this paper.