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Compact Q-band low noise amplifier modules using 0.1 pm InGaAsAnAAsAnP HEMT MMTCs have been demonstrated with high performance and high manufacturability over a frequency band from 43.5 to 45.5 GHz at Northrop Grurnman Space Technology (NGST). The compact InP HEMT LNAs and modules are essential for phased-array applications. The LNA modules demonstrate noise figure less than 2.5 dB over the frequency band of 43.5 to 45.5 GHz The RF performance results achieved here, in conjunction with previously reported high reliability results, further demonstrate the readiness of NGST's 0. I pm TnP HEMT MMlC technology for advanced phased-array applications. In addition, Ig de-bias effect induced failure (DBIF) was observed on InP HEMT MMlCs with stacked cascode configuration subjected to elevated temperature lifetest. Accordingly, an acceptable lifetest temperature window was found to alleviate DBIF while performing Iifetest on InP HEMT MMICs with stacked cascode configuration.

We present state-of-the-art power and PAE results of InGaAs/InAlAs/InP HEMTs with optimized graded channel and graded Schottky barrier layers which demonstrate, for the first time, that Inpbased HEMTs have a considerably better powerPAE combination than GaAs-based HEMTs at Vband. The 0.15 pm gate length, eight gate finger, 500 pm wide InP HEMTs were measured in fixture under continuous wave (CW) conditions and showed 23 dBm (200 mW) output power and 40% PAE at 60 GHz with an input power of 17 dBm, a drain bias of 3 V, and a drain current of 125 mA. Figure 1 shows the measured output power, power gain, and PAE versus input power at 60 GHz for the fixtured and tuned device. These results represent the best reported V-band power/PAE performance to date, and a comparison of these results with previously reported results [ 1-51 for both InP-and GaAs-based HEMTs is shown in Figure 2. Our state-of-the-art results are attributed to the use of an optimized heterostructure incorporating pseudomorphic graded channel and graded Schottky barrier layers, and the use of compact 15 pm x 25 pm dry etched throughsubstrate vias (substrate thickness of 50 pm).The heterostructure was designed to achieve high gain, current (Imax), and breakdown voltage; all of which are requirements for a device with high power and PAE. A series of experiments was conducted in which variations were made to the channel layer, Schottky barrier layer, cap layer, and the doping planes. A schematic of the layer structures is shown in Figure 3, and the details of the variations, as well as the optimal design, will be presented. The optimal design improved the Imax by 17%, the off-state reverse gate drain breakdown voltage by 55%, the transconductance (Gm) by 23%, the fT by 30%, and the fmax by 13%, compared to a similar structure consisting of lattice matched InGaAshAlAs.Device performance was enhanced further by using extremely compact 15 pm x 25 pm slot vias that are etched through the 50 pm-thick substrate. The vias connect each of the frontside source pads to the backside ground plane, and are etched using an HBr/BCls-based plasma. A cross-section of the vias is shown in Figure 4. The use of dry etched slot vias 1.) compacts the device thereby reducing combining losses, 2.) improves thermal properties by increasing finger spacing, and 3.) reduces the source inductance; all of which are desirable for high power and PAE. Figure 5 shows a comparison of the layout of an eight finger 500 pm wide device that has five dry etched vias and a 500 vm wide device that has three wet etched vias. The power and PAE performance of devices with wet etch vias will be provided for comparison with the devices having dry etch vias to show the enhanced device performance achieved by using the dry etched vias.