The packaging process can increase the driving force for interfacial delamination and significantly impacts the reliability of the low k chip. In this study we investigated the packaging effect due to die attach process where a high thermal load occurs during solder reflow before underfilling. With the high thermal load and without the underfill, the chip-package interaction is maximized and can become most detrimental to low k chip reliability. Both SiLK and MSQ dielectrics were investigated to examine the influence of low k properties on packaging reliability. In addition to different low k dielectrics, we investigated the effects due to the substrate material, die size and solder materials, including the lead-free solder. The packaging effect was found to be higher for flip-chip packages with lead-free solder than the eutectic lead solder and the high lead solders. Flip-chip packages with a ceramic substrate were found to have a smaller packaging effect than that with a plastic substrate. Increasing die size increases the crack driving force for low k interfacial delamination, as expected. Packaging effect was generally lower for the Cu/MSQ structure than for the Cu/SiLK structure, and the difference can be attributed to the higher Young's modulus of the MSQ material.