Chip-Packaging Interaction and Reliability Impact on Cu/Low k Interconnects

Abstract

The packaging process can increase the driving force for interfacial delamination and significantly impacts the reliability of the low k chip. In this study we investigated the packaging effect due to die attach process where a high thermal load occurs during solder reflow before underfilling. With the high thermal load and without the underfill, the chip-package interaction is maximized and can become most detrimental to low k chip reliability. Both SiLK and MSQ dielectrics were investigated to examine the influence of low k properties on packaging reliability. In addition to different low k dielectrics, we investigated the effects due to the substrate material, die size and solder materials, including the lead-free solder. The packaging effect was found to be higher for flip-chip packages with lead-free solder than the eutectic lead solder and the high lead solders. Flip-chip packages with a ceramic substrate were found to have a smaller packaging effect than that with a plastic substrate. Increasing die size increases the crack driving force for low k interfacial delamination, as expected. Packaging effect was generally lower for the Cu/MSQ structure than for the Cu/SiLK structure, and the difference can be attributed to the higher Young's modulus of the MSQ material.

Structural effects on Chip Package Interaction and mechanical reliability of Cu/low-k multi-layer interconnects in flip-chip package

“…2. At the interconnect level, the Energy Release Rate (ERR) is calculated as the driving force for the interfacial delamination using Modified Virtual Crack Closure (MVCC) technique [5].…”

“…The mismatch in thermal expansion/shrinkage between chip and package can lead to significant deformation, both locally and globally. The local stress due to Chip Package Interaction (CPI) can cause peeling and drives the interfacial delamination in Cu/low-k interconnects, and this raises serious reliability concern [2][3][4][5]. Thermomechanical stability is a serious issue for microelectronic packaging, its impact to product yield and manufacturing cost intensifies as low-k dielectrics and leadfree solders are being adopted by the industry.…”

Planar Microspring—A Novel Compliant Chip-to-Package Interconnect for Wafer-Level Packaging

“…With the increasing utilization of low-dielectric to enhance signal transmission speed, delamination between these dielectrics and metallization has been frequently observed as a result of either poor adhesion or coupled deformation of chip and substrate during assembly and packaging [23]. To relieve the stress accumulated in the dielectric, a compliant interconnect structure [24] was fabricated by first forming a polymeric dome by photolithography and then electroplating to create 3-D interconnection structure, as shown in Fig.…”