The use of multi-phase clotilng scheme, aggressive pipelining and "sparse" encodings in high performance designs results in a tremendous increase in the state space. In this paper, we show that automatically transforming such dwigns to ones that have more "dense" encodings can result in significant benefits in using implicit BDD-based techniques for their verification. We formulate a relaxed retiming framework which is more powerful than traditional retiming in reducing the number of latches and show' that it can be applied to the product machine model for cheWlng sequential hardwae equitience (SHE) without altering the correctness of the SHE check. We combine retiming v.tithphase abstraction [4] (a technique to transform multi-phase FShls to singlephase FSMS for equidence checking). The tivo transformations enable the SHE check to be performed on high performance controllers with large state space (more than 100 latches) from an industrid setting.

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Simulated annealing is an effective tool in many optimization problems in VLSI CAD but its time requirements are prohibitive. In this paper, we report parallel algorithms for a well established simulated annealing based algorithm for the state assignment problem for finite state machines. Our parallel annealing strategy uses parallel moves by multiple processes, each performing local moves within its assigned subspace of the state encoding space. The novelty is in the dynamic repartitioning of the state space among processors, so that each processor gets to perform moves on the entire space over time. This is important to keep the quality of the parallel algorithm comparable to the serial algorithm. Our algorithm gives quality results within 0.05% of the serial algorithm on 64 processors. Our algorithms, Proper-JEDI and PartJEDI, are portable across a wide range of MIMD machines. PartJEDI is memory scalable and is incrementally developed from ProperJEDI which is data replicated. For a large circuit, ProperJEDI reduces the runtime from 11 h to 10 min on a 64-processor machine. For the same circuit, PartJEDI reduces the runtime from 11 h to 20 min and memory requirement from 114 to 2 MB.

Binary Decision Diagrams (BDDs) often fail to exploit sharing between Boolean functions that differ only in their support variables. In a memory circuit, for example, the functions for the different bits of a word differ only in the data bit while the address decoding part of the function is identical. We present a symbolic representation approach using ordered function templates to exploit such regularity.Templates specify functionality without being bound to a specific set of variables. Functions are obtained by instantiating templates with a list of variables. We ensure canonicity of the representation by requiring that templates are normalized and argument lists are ordered. We also present algorithms for performing Boolean operations using this representation. Experiments with a prototype implementation built on top of CUDD indicate that function templates can dramatically reduce memory requirements for symbolic simulation of regular circuits.interest. Edge attributes further reduce the size requirements. In [10], the authors proposed three edge-attributes to reduce the size of the shared DAG: