Efficient equivalence checking of multi-phase designs using retiming

Abstract

The use of multi-phase clotilng scheme, aggressive pipelining and "sparse" encodings in high performance designs results in a tremendous increase in the state space. In this paper, we show that automatically transforming such dwigns to ones that have more "dense" encodings can result in significant benefits in using implicit BDD-based techniques for their verification. We formulate a relaxed retiming framework which is more powerful than traditional retiming in reducing the number of latches and show' that it can be applied to the product machine model for cheWlng sequential hardwae equitience (SHE) without altering the correctness of the SHE check. We combine retiming v.tithphase abstraction [4] (a technique to transform multi-phase FShls to singlephase FSMS for equidence checking). The tivo transformations enable the SHE check to be performed on high performance controllers with large state space (more than 100 latches) from an industrid setting.

Register Transformations with Multiple Clock Domains

“…In the first example (Fig. 4), we demonstrate how Hasteer et al's [10] phase abstraction can be viewed in our framework. This example circuit is taken from their paper.…”

“…Hasteer et al [10] concentrate on k-phase, level-sensitive clocking, where there are k non-overlapping clocks, all with the same frequency, and introduce the concept of phase abstraction, in which all but one phase of registers is eliminated. The resulting circuit has 1/k as many registers, reducing the state space of the circuit for verification purposes.…”

Transformation-Based Verification Using Generalized Retiming

“…Proof. First we show that function (8) correcly maps { C, S} to C: For t < w(u, v) − r(v), (8) reflects the definition of s given in (6). For t ≥ wuv − r(v), after substitution using (5), we must show that…”

“…The application of structural circuit transformations in sequential verification is a relatively new research area. Hasteer et al [8] proposed the concepts of retiming and state space folding for sequential equivalence checking. Their state-folding technique works for circuits in which the number of latches contained in loops and reconverging paths is constant modulo n. In this case n succeeding state transitions can be concatenated for symbolic state traversal.…”

“…In essence, formula (8) provides the mechanism for trace lifting that back-translates any counter example from the retimed circuit to the original circuit.…”