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This paper demonstrates the effectiveness and advantages of ULP (Ultra-Low-Power) MOS diodes vs. standard implementations of a AC-DC voltage multipler in a 150nm multiple-threshold voltage SOI CMOS technology for RFID applications. Introducing a specific design methodology, we compare two 3 stages voltage multipliers, each using one of those diodes types and driving a 1.5μA load. Both architectures use an input signal of 1V peak to peak and 13.56MHz carrier frequency. Efficiency, output voltage, temperature and current load as well as backgate voltage influences are analyzed theoretically and experimentally. The ULP implementation reaches much better output voltage and efficiency than the standard one, by 70% and a factor of 6 respectively under nominal conditions.