We present artificial neural network design using spin devices that achieves ultra low voltage operation, low power consumption, high speed, and high integration density. We employ spin torque switched nano-magnets for modelling neuron and domain wall magnets for compact, programmable synapses. The spin based neuron-synapse units operate locally at ultra low supply voltage of 30mV resulting in low computation power. CMOS based inter-neuron communication is employed to realize network-level functionality. We corroborate circuit operation with physics based models developed for the spin devices. Simulation results for character recognition as a benchmark application shows 95% lower power consumption as compared to 45nm CMOS design.

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A simulation framework that can comprehend the impact of material changes from the device level to the system level design can be of great value, especially to evaluate the impact of emerging devices on various applications. To that effect, we developed a SPICE-based hybrid magnetic tunnel junction (MTJ)/CMOS simulator, which can be used to explore new opportunities in large scale system design. In the proposed simulation framework, MTJ modeling is based on Landau-Lifshitz-Gilbert (LLG) equation incorporating both spin-torque and external magnetic field(s). LLG, along with heat diffusion equation, thermal variations, and electron transport, is implemented using SPICE-inbuilt voltage-dependent current sources and capacitors. The proposed simulation framework is flexible because the physical device parameters such as MgO thickness, ferromagnet material anisotropy (K u ), and device dimensions are user-defined parameters. Furthermore, we benchmarked this model with experiments in terms of switching current density ( J C ), switching time (T SWITCH ), and tunneling magnetoresistance. Finally, we used the simulation framework to study different MTJ structures, such as in-plane magnet anisotropy and perpendicular magnet anisotropy, the impact of parametric process variations and temperature on the yield of spin transfer torque magnetoresistive random access memories, magnetic flip-flops, and spin-torque oscillators.Index Terms-Compact model, hybrid design, magnetic flip-flops (MFF), magnetic tunnel junction (MTJ), simulation framework, SPICE, spin-torque oscillators (STO), spin transfer torque magnetoresistive random access memory (STT-MRAM).

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