The purpose of this paper is to formally specify a flow devoted to the design of Differential Power Analysis (DPA) resistant QDI asynchronous circuits. The paper first proposes a formal modeling of the electrical signature of QDI asynchronous circuits. The DPA is then applied to the formal model in order to identify the source of leakage of this type of circuits. Finally, a complete design flow is specified to minimize the information leakage. The relevancy and efficiency of the approach is demonstrated using the design of an AES crypto-processor. Asy nchronous Module Asy nchronous Module Request Acknowledgement Request Request Acknowledgement Acknowledgement Asy nchronous Module Asy nchronous Module Request Acknowledgement Request Request Acknowledgement Acknowledgement Fig. 1: Handshake based communication between modules. A module can actually be of any complexity.
This paper presents a concrete evaluation of Quasi Delay Insensitive (QDI) Asynchronous logic in terms of current consumption within a wide range of supply voltages. The designed and fabricated circuit is a QDI Advanced Encryption Standard (AES) crypto-processor, compliant with the NIST standard FIPS197. This circuit exploits fundamental properties of the QDI Asynchronous logic, especially delay insensitivity, to enable relaxed operating conditions. The circuit, powered at 1.2 volt, ciphers a 128 bit data using a 128 bit key in 910 ns which corresponds to a ciphering rate of 141 Mbits per second. Due to the robustness of the clock-less QDI logic, the circuit is functional within a wide voltage range, down to 0.4 Volt. With such a low supply voltage the chip consumes 200 µA sustaining a ciphering data rate of 6.4 Mbits/s. Moreover, clock-less circuits also generate less electromagnetic noise. This work demonstrates that QDI asynchronous logic is particularly interesting in secure, low-voltage, low-power and low-noise applications. These properties are clearly suitable to address different markets such as smartcard and mobile phones.
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