Here we evaluate in-situ Ga doping of SiGe as an alternative to ex-situ ion implantation for source/drain contact formation. Si0.5Ge0.5 layers are grown on an ASM Intrepid ES high volume CVD reactor and co-doped with B and Ga. A circular transmission line measurement (CTLM) comparison of SiGe:B and SiGe:B:Ga is presented and we report a statistically significant improvement in contact resistivity with the addition of Ga. The Ti/SiGe contacts formed with the B-doped sample had an average ρc ~ 9 x 10-9 Ω-cm2 while the best Ga/B co-doped sample yielded an average ρc ~ 2.5 x 10-9 Ω-cm2. We also evaluate the epitaxial growth on fin patterned wafers and we are able to demonstrate high crystalline quality SiGe:Ga layers without loss of selectivity on the dielectric areas of the wafer.

This contribution focuses on S/D epitaxial layers grown and in-situ doped by chemical vapor deposition, and on the properties of fabricated Ti/p-Si1-xGex contacts. The Ti/Si1-xGex:B contact resistivity and the Si1-xGe1-x:B layer resistivity are both minimized for an optimized range of layer thickness. Both parameters increase as the layer relaxes. Preserving strain in Si1-xGex:B S/D material is therefore important. The increase in S/D layer resistivity and contact resistivity with increasing layer thickness is, however, not caused by the (small) increase in electrical band gap induced by (partial) layer relaxation. Instead, B incorporation during epitaxial growth is affected by the initiation of layer relaxation and decreases with increasing degree of strain relaxation. This effect is observed for the whole range of Ge concentrations. The reduced B incorporation results in a lower carrier concentration near the layer surface which, in-turn, explains the increase in contact resistivity and layer resistivity.

We describe challenges of the epitaxial Si-cap/Si0.75Ge0.25//Si-substrate growth process, in view of its application in 3D device integration schemes using Si0.75Ge0.25 as backside etch stop layer with a focus on high throughput epi processing without compromising material quality. While fully strained Si0.75Ge0.25 with a thickness >10 times larger than the theoretical thickness for layer relaxation can be grown, it is challenging to completely avoid misfit dislocations at the wafer edge during Si-growth on top of strained Si0.75Ge0.25, even for thinner Si0.75Ge0.25 layers and when growing the Si-cap layer at a lower temperature. Extremely sensitive characterization methods are mandatory to detect the extremely low density of misfit dislocations at the wafer edge. Light scattering measurements are most reliable. The epitaxial Si-cap/Si0.75Ge0.25//Si-substrate layer stacks are stable against post-epi thermal processing steps, typically applied before wafer-to-wafer bonding and Si-substrate and Si0.75Ge0.25 backside removal.